Intel X5675 BX80614X5675 Manuale Utente
Codici prodotto
BX80614X5675
Intel
®
Xeon
®
Processor 5600 Series Datasheet Volume 1
51
Electrical Specifications
Notes:
1.
Unless otherwise noted, all specifications in this table apply to all processor frequencies. Timing
specifications only depend on the operating frequency of the memory channel and not the maximum rated
frequency.
2.
When the single ended slew rate of the input Data or Strobe signals, within a byte group, are below 1.0
V/ns, the tSU and tHD specifications must be increased by a derating factor. The input single ended slew
rate is measured DC to AC levels; V
IL
_DC to V
IH
_AC for rising edges, and V
IH
_DC to V
IL
_AC for falling
edges. Use the worse case minimum slew rate measured between Data and Strobe, within a byte group, to
determine the required derating value. No derating is required for single ended slew rates equal to or
greater than 1.0 V/ns.
3.
Edge Placement Accuracy (EPA): The silicon contains digital logic that automatically adjusts the timing
relationship
between the DDR reference clocks and DDR signals. The BIOS initiates a training procedure
that will place a given
signal appropriately within the clock period. The difference in delay between the
signal and clock is accurate to
within +/- EPA. This EPA includes jitter, skew, within die variation and several
other effects.
4.
Data to Strobe read setup and Data from Strobe read hold minimum requirements specified at the
processor pad are determined with the minimum Read DQS/DQS# delay.
5.
C
WL
(CAS Write Latency) is the delay, in clock cycles, between the rising edge of CK where a write
command is referenced and the first rising strobe edge where the first byte of write data is present. The
C
WL
value is determined by the value of the CL (CAS Latency) setting.
6.
The system memory clock outputs are differential (CLK and CLK#), the CLK rising edge is referenced at the
crossing point where CLK is rising and CLK# is falling.
7.
The system memory strobe outputs are differential (DQS and DQS#), the DQS rising edge is referenced at
the crossing point where DQS is rising and DQS# is falling, and the DQS falling edge is referenced at the
crossing point where DQS is falling and DQS# is rising.
8.
This values specifies the parameter after write leveling, representing the residual error in the controller
after training, and does not include any effects from the DRAM itself.
T
DQS_CO
DQS Edge Placement Accuracy to
CK Rising Edge AFTER write
leveling
+275
-275
ns
3,6,7,8
T
WPRE
DQS/DQS# Write Preamble
Duration
2.379
ns
T
WPST
DQS/DQS# Write Postamble
Duration
1.371
1.129
ns
T
DQSS
CK Rising Edge Output Access
Time, Where a Write Command Is
Referenced, to the First DQS Rising
Edge
C
WL
x (T
CK
+ 4)
ns
5,6
Table 2-23. DDR3/DDR3L Electrical Characteristics and AC Specifications at 800 MT/s
(Sheet 2 of 2)
Symbol
Parameter
Channel 0
Channel 1
Channel 2
Unit
Figure
Note
Max
Min
Table 2-24. DDR3 Electrical Characteristics and AC Specifications at 1066 MT/s (Sheet 1
of 2)
Symbol
Parameter
Channel 0
Channel 1
Channel 2
Unit
Figure
Note
Max
Min
Latency Timings
tCL – tRCD – tRP
CAS Latency – RAS to CAS Delay –
Pre-charge Command Period
7 – 7 – 7
8 - 8 - 8
tCK
Electrical Characteristics
T
SLR_D
DQ[63:0], DQS_P[17:0],
DQS_N[17:0], ECC[7:0]
Input Slew Rate
Input Slew Rate
4.0
1.0
V/ns
2