u-blox AG VERAP174 Manuale Utente
VERA-P1 series - Data Sheet
UBX-17004377 - R06_draft
Confidential
Host interfaces
Page 7 of 30
2 Host interfaces
2.1 USB interface
The VERA-P1 series module supports a USB 2.0 high-speed interface for firmware loading (booting)
and high speed data transfer (> 200 Mbps). The USB interface of the module is powered with 3.3 V
supply voltage. The module acts as a device on the USB bus.
and high speed data transfer (> 200 Mbps). The USB interface of the module is powered with 3.3 V
supply voltage. The module acts as a device on the USB bus.
2.2 SPI interface
The VERA-P1 series module supports an SPI interface for firmware loading (booting) and data
communication. Firmware can be loaded by the host processor while the module operates as a slave
or from the FLASH memory while the module is in the master mode. The interface is capable of full-
duplex operation in master or slave mode. The maximum clock rate is 50 MHz in master mode, and
25 MHz in slave mode
communication. Firmware can be loaded by the host processor while the module operates as a slave
or from the FLASH memory while the module is in the master mode. The interface is capable of full-
duplex operation in master or slave mode. The maximum clock rate is 50 MHz in master mode, and
25 MHz in slave mode
3
.
⚠
Due to performance limitations, it is recommended not to use the SPI interface as the main host
interface for communication and operation of the module.
interface for communication and operation of the module.
3 SPI host interface for data communication in slave mode is tested only with 15 MHz clock rate.