Intel X5675 AT80614006696AA Manuale Utente
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AT80614006696AA
Electrical Specifications
26
Intel
®
Xeon
®
Processor 5600 Series Datasheet Volume 1
Notes:
1.
When the “11111111” VID pattern is observed, or when the SKTOCC# pin is pulled high, the voltage
regulator output should be disabled.
2.
The VID range includes VID transitions that may be initiated by thermal events, Extended HALT state
transitions (see
), higher C-States (see
) or Enhanced Intel SpeedStep
®
Technology
transitions (see
). The Extended HALT state must be enabled for the processor to
remain within its specifications
3.
Once the VRM/EVRD is operating after power-up, if either the Output Enable signal is de-asserted or a
specific VID off code is received, the VRM/EVRD must turn off its output (the output should go to high
impedance) within 500 ms and latch off until power is cycled.
2.1.7.3.1
Power-On Configuration (POC) Logic
VID[7:0] signals also serve a second function. During power-up, Power-On
Configuration POC[7:0] logic levels are MUX’ed onto these signals via 1-5 k pull-up or
pull down resistors located on the baseboard. These values provide voltage regulator
keying (VID[7]), inform the processor of the platforms power delivery capabilities
(MSID[2:0]), and program the gain applied to the ISENSE input (CSC[2:0]).
Configuration POC[7:0] logic levels are MUX’ed onto these signals via 1-5 k pull-up or
pull down resistors located on the baseboard. These values provide voltage regulator
keying (VID[7]), inform the processor of the platforms power delivery capabilities
(MSID[2:0]), and program the gain applied to the ISENSE input (CSC[2:0]).
maps VID signals to the corresponding POC functionality.
Note:
1.
This setting is defined for future use; no Intel Xeon processor 5600 series SKU is defined with ICC_MAX=40
A.
2.
In general, set PWM IMON slope to 900 mV = IMAX, where IMAX = ICCMAX. For the 130 W SKU, set IMON
slope to 900 mV= 180 A. All other SKUs must match the values shown above. Please consult the PWM
datasheet for the IMON slope setting.
Some POC signals include specific timing requirements. Please refer to
for
further details.
1
0
1
1
0
0
1
0
0.50000
1
1
1
1
1
1
1
0
OFF
1
1
1
1
1
1
1
1
OFF
Table 2-2.
Voltage Identification Definition (Sheet 6 of 6)
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
V
CC_MAX
Table 2-3. Power-On Configuration (POC[7:0]) Decode
Function
Bits
POC Settings
Description
VR_Key
VID[7]
0b for VR11.1
Electronic safety key
distinguishing VR11.1
Spare
VID[6]
0b (default)
Reserved for future use
CSC[2:0]
VID[5:3]
-000b
-001b
-010b
-011b
-100b
-101b
-111b
-001b
-010b
-011b
-100b
-101b
-111b
Feature Disabled
ICC_MAX 40 A
1
40 W TDP / ICC_MAX 50 A
60 W TDP / ICC_MAX = 80 A
80W TDP / ICC_MAX = 100 A
95W TDP / ICC_MAX = 120 A
95W TDP / ICC_MAX = 120 A
130W TDP / ICC_MAX =
150A
2
Current Sensor Configuration
(CSC) programs the gain
applied to the ISENSE A/D
output. ISENSE data is then
used to dynamically calculate
current and power.
MSID[2:0]
VID[2:0]
-001b
-011b
-100b
-101b
-110b
-011b
-100b
-101b
-110b
40 W TDP / 50 A ICC_MAX
60 W TDP / 80 A ICC_MAX
60 W TDP / 80 A ICC_MAX
80 W TDP / 100 A ICC_MAX
95 W TDP / 120 A ICC_MAX
95 W TDP / 120 A ICC_MAX
130 W TDP / 150 A ICC_MAX
MSID[2:0] signals are provided
to indicate the Market Segment
for the processor and may be
used for future processor
compatibility or keying. See
for platform timing
requirements of the MSID[2:0]
signals.