ZTE Corporation ZM8300G Manuale Utente
ZTE ZM8300G Module Hardware User Manual
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following characteristics:
1) The UART_DM interface supports high-speed UART running, with the maximum rate
reaching 4 Mbit/s.
2) Strengths of the UART_DM block: The RX and TX rate control data movers have
separate CRCI channels. An SRAM can achieve a large RX and TX FIFOX and obtain a fast
system bus (AHB interface). When the data movers are unavailable, the traditional interrupt is
directly saved to the microprocessor.
3) The TX and RX channels of a UART_DM interface primarily differ from those of a basic
UART interface in the following aspects:
a) FIFO is implemented in the SRAM.
b) FIFO control and IRQ generation are implemented in the DM control block.
4) The UART interfaces can be used as diagnostic interfaces.
Note that the UART level of ZM8300G is 1.8V. If external AP interface is 3.3V, the level
shifting circuit is applied(level shifting IC:TXB0104RUTR) when ZM8300G carry out AT
communication. The reference design circuit for UART is showed as FIG3-9
ZM8300
Level
Shift
AP
VIO
VCCA
OE
VCCB
GND
VCC_3V3
U
A
R
T
(1
.8
v
)
A1~A4
GND
GND
B1~B4
U
A
R
T
(3
.3
v
)
Figure 3-9 UART Reference Circuit
3.6.3
SPI Bus Interface
The SPI is a four-wire (MISO, MOSI, CS, and CLK) synchronous serial data link. The SPI bus
interface has the following characteristics:
1) When the SPI bus interface works as the master device, the clock frequency of BLSPA
can reach 50 MHz and that of BLSPB can reach 38 MHz.
2) When the SPI bus interface initiates data transmission as the master device, multiple
slave devices can be supported by means of the chip select (CS) signal.
3) Explicit communication framing, error checking, and defined data word lengths are
absent. Therefore, data transmission must strictly observe the raw bit level.
4) When working as the SPI master device, the SPI bus interface supports the following