Getac Technology Corporation V110GD Manuale Utente

Pagina di 320
PIC32MX1XX/2XX
DS61168C-page 128
Preliminary
© 2011 Microchip Technology Inc.
 
REGISTER 10-6:
U1IR: USB INTERRUPT REGISTER
Bit 
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
23:16
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
15:8
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
7:0
R/WC-0, HS
R/WC-0, HS
R/WC-0, HS
R/WC-0, HS
R/WC-0, HS
R/WC-0, HS
R-0
R/WC-0, HS
STALLIF
ATTACHIF
(1)
RESUMEIF
(2)
IDLEIF
TRNIF
(3)
SOFIF
UERRIF
(4)
URSTIF
(5)
DETACHIF
(6)
Legend:
WC = Write ‘1’ to clear
HS = Hardware Settable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-8 Unimplemented: Read as ‘0’
bit 7
STALLIF:
 STALL Handshake Interrupt bit
1
 = In Host mode a STALL handshake was received during the handshake phase of the transaction
In Device mode a STALL handshake was transmitted during the handshake phase of the transaction
0
 = STALL handshake has not been sent
bit 6
ATTACHIF:
 Peripheral Attach Interrupt bit
(1)
1
 = Peripheral attachment was detected by the USB module
0
 = Peripheral attachment was not detected
bit 5
RESUMEIF: 
Resume Interrupt bit
(2)
1
 = K-State is observed on the D+ or D- pin for 2.5 µs
0
 = K-State is not observed
bit 4
IDLEIF:
 Idle Detect Interrupt bit
1
 = Idle condition detected (constant Idle state of 3 ms or more)
0
 = No Idle condition detected
bit 3
TRNIF:
 Token Processing Complete Interrupt bit
(3)
1
 = Processing of current token is complete; a read of the U1STAT register will provide endpoint information
0
 = Processing of current token not complete
bit 2
SOFIF:
 SOF Token Interrupt bit
1
 = SOF token received by the peripheral or the SOF threshold reached by the host
0
 = SOF token was not received nor threshold reached
bit 1
UERRIF: 
USB Error Condition Interrupt bit
(4)
1
 = Unmasked error condition has occurred
0
 = Unmasked error condition has not occurred
Note 1:
This bit is valid only if the HOSTEN bit is set (see 
), there is no activity on the USB for 
2.5 µs, and the current bus state is not SE0.
2:
When not in Suspend mode, this interrupt should be disabled.
3:
Clearing this bit will cause the STAT FIFO to advance.
4:
Only error conditions enabled through the U1EIE register will set this bit.
5:
Device mode.
6:
Host mode.