Getac Technology Corporation V110GD Manuale Utente
PIC32MX1XX/2XX
DS61168C-page 156
Preliminary
© 2011 Microchip Technology Inc.
FIGURE 13-2:
TIMER2/3, 4/5 BLOCK DIAGRAM (32-BIT)
(1)
TMRy
TMRx
TyIF Event
Equal
32-bit Comparator
PRy
PRx
Reset
LS Half Word
MS Half Word
Flag
Note 1:
In this diagram, the use of ‘x’ in registers, TxCON, TMRx, PRx and TxCK, refers to either Timer2 or
Timer4; the use of ‘y’ in registers, TyCON, TMRy, PRy, TyIF, refers to either Timer3 or Timer5.
Timer4; the use of ‘y’ in registers, TyCON, TMRy, PRy, TyIF, refers to either Timer3 or Timer5.
2:
ADC event trigger is available only on the Timer2/3 pair.
TGATE
0
1
PBCLK
Gate
TxCK
Sync
Sync
ADC Event
Trigger
(2)
ON
TGATE
TCS
TCKPS
Prescaler
3
1, 2, 4, 8, 16,
32, 64, 256
1
0
0
0
Q
Q
D
x
1