Getac Technology Corporation V110GD Manuale Utente

DS61168C-page 176

© 2011 Microchip Technology Inc.

bit 7

 General Call Enable bit (when operating as I

2

C slave)

1

 = Enable interrupt when a general call address is received in the I2CxRSR

(module is enabled for reception)

0

 = General call address disabled

bit 6

 SCLx Clock Stretch Enable bit (when operating as I

2

C slave)

Used in conjunction with SCLREL bit.
1

 = Enable software or receive clock stretching

0

 = Disable software or receive clock stretching

bit 5

 Acknowledge Data bit (when operating as I

2

C master, applicable during master receive)

Value that is transmitted when the software initiates an Acknowledge sequence.
1

 = Send NACK during Acknowledge

0

 = Send ACK during Acknowledge

bit 4

 Acknowledge Sequence Enable bit 

(when operating as I

2

C master, applicable during master receive)

1

 = Initiate Acknowledge sequence on SDAx and SCLx pins and transmit ACKDT data bit. 

Hardware clear at end of master Acknowledge sequence.

0

 = Acknowledge sequence not in progress

bit 3

 Receive Enable bit (when operating as I

2

C master)

1

 = Enables Receive mode for I

2

C. Hardware clear at end of eighth bit of master receive data byte.

0

 = Receive sequence not in progress

bit 2

 Stop Condition Enable bit (when operating as I

2

C master)

1

 = Initiate Stop condition on SDAx and SCLx pins. Hardware clear at end of master Stop sequence.

0

 = Stop condition not in progress

bit 1

 Repeated Start Condition Enable bit (when operating as I

2

C master)

1

 = Initiate Repeated Start condition on SDAx and SCLx pins. Hardware clear at end of 

master Repeated Start sequence.

0

 = Repeated Start condition not in progress

bit 0

 Start Condition Enable bit (when operating as I

2

C master)

1

 = Initiate Start condition on SDAx and SCLx pins. Hardware clear at end of master Start sequence.

0

 = Start condition not in progress

When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the 
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.