Getac Technology Corporation V110GD Manuale Utente
PIC32MX1XX/2XX
DS61168C-page 186
Preliminary
© 2011 Microchip Technology Inc.
REGISTER 19-1:
PMCON: PARALLEL PORT CONTROL REGISTER
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
23:16
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
15:8
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ON
(1)
—
SIDL
ADRMUX<1:0>
PMPTTL
PTWREN
PTRDEN
7:0
R/W-0
R/W-0
R/W-0
U-0
R/W-0
U-0
R/W-0
R/W-0
CSF<1:0>
(2)
ALP
(2)
—
CS1P
(2)
—
WRSP
RDSP
Legend:
R = Readable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15
bit 15
ON:
Parallel Master Port Enable bit
(1)
1
= PMP enabled
0
= PMP disabled, no off-chip access performed
bit 14
Unimplemented:
Read as ‘0’
bit 13
SIDL:
Stop in Idle Mode bit
1
= Discontinue module operation when device enters Idle mode
0
= Continue module operation in Idle mode
bit 12-11 ADRMUX<1:0>: Address/Data Multiplexing Selection bits
11
= Lower 8 bits of address are multiplexed on PMD<7:0> pins; upper 8 bits are not used
10
= All 16 bits of address are multiplexed on PMD<7:0> pins
01
= Lower 8 bits of address are multiplexed on PMD<7:0> pins, upper bits are on PMA<10:8> and
PMA<14>
00
= Address and data appear on separate pins
bit 10
PMPTTL:
PMP Module TTL Input Buffer Select bit
1
= PMP module uses TTL input buffers
0
= PMP module uses Schmitt Trigger input buffer
bit 9
PTWREN:
Write Enable Strobe Port Enable bit
1
= PMWR/PMENB port enabled
0
= PMWR/PMENB port disabled
bit 8
PTRDEN:
Read/Write Strobe Port Enable bit
1
= PMRD/PMWR port enabled
0
= PMRD/PMWR port disabled
bit 7-6
CSF<1:0>:
Chip Select Function bits
(2)
11
= Reserved
10
= PMCS1 function as Chip Select
01
= PMCS1 functions as address bit 14
00
= PMCS1 function as address bit 14
bit 5
ALP:
Address Latch Polarity bit
(2)
1
= Active-high (PMALL and PMALH)
0
= Active-low (PMALL and PMALH)
Note 1:
When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON control bit.
SYSCLK cycle immediately following the instruction that clears the module’s ON control bit.
2:
These bits have no effect when their corresponding pins are used as address lines.