Getac Technology Corporation V110GD Manuale Utente
© 2011 Microchip Technology Inc.
Preliminary
DS61168C-page 87
PIC32MX1XX/2XX
7.0
INTERRUPT CONTROLLER
PIC32MX1XX/2XX devices generate interrupt requests
in response to interrupt events from peripheral modules.
The interrupt control module exists externally to the CPU
logic and prioritizes the interrupt events before
presenting them to the CPU.
in response to interrupt events from peripheral modules.
The interrupt control module exists externally to the CPU
logic and prioritizes the interrupt events before
presenting them to the CPU.
The PIC32MX1XX/2XX interrupt module includes the
following features:
• Up to 64 interrupt sources
• Up to 44 interrupt vectors
• Single and multi-vector mode operations
• Five external interrupts with edge polarity control
• Interrupt proximity timer
• Seven user-selectable priority levels for each
following features:
• Up to 64 interrupt sources
• Up to 44 interrupt vectors
• Single and multi-vector mode operations
• Five external interrupts with edge polarity control
• Interrupt proximity timer
• Seven user-selectable priority levels for each
vector
• Four user-selectable subpriority levels within each
priority
• Dedicated shadow set for all priority levels
(1)
• Software can generate any interrupt
• User-configurable interrupt vector table location
• User-configurable interrupt vector spacing
• User-configurable interrupt vector table location
• User-configurable interrupt vector spacing
FIGURE 7-1:
INTERRUPT CONTROLLER MODULE
Note 1:
This data sheet summarizes the features
of the PIC32MX1XX/2XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 8. “Interrupt
Controller”
of the PIC32MX1XX/2XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 8. “Interrupt
Controller”
(DS61108) in the “PIC32
Family Reference Manual”
, which is
www.microchip.com/PIC32
).
2:
Some registers and associated bits
described in this section may not be
available on all devices. Refer to
described in this section may not be
available on all devices. Refer to
in
this data sheet for device-specific register
and bit information.
and bit information.
Note 1:
On PIC32MX1XX/2XX devices, the
dedicated shadow set is associated with
all priority levels.
dedicated shadow set is associated with
all priority levels.
Interrupt Controller
Inter
rupt Re
quest
s
Vector Number
CPU Core
Priority Level
Shadow Set Number