Honeywell International Inc. RTA-50D Manuale Utente

MAINTENANCE MANUAL

965-1696

(6)

ARINC 429 I/O Circuitry

(a)

The ARINC 429 I/O transmitter encoding and receiver decoding logic is implemented
in an Actel ProASIC Plus flash FPGA with 600,000 gates. Digital logic-to-CMOS level
translation circuits are provided externally for each transmitter and receiver.

(b)

The ARINC429 I/O FPGA interfaces to the MPC8250 through a PCI bus interface. The
ARINC 429 I/O FPGA supports 4 ARINC 429 transmitters and 11 ARINC 429 receivers
with automatic speed detection.

(c)

The ARINC 429 transmitters are used to do the following functions:

• Data link output high-speed transmitter

• OMS output low-speed transmitter

• Two spare transmitters.

(d)

The ARINC 429 receivers are used to do the following functions:

• Two frequency select tuning input receivers

• Two data link input receivers

• Two OMS input receivers

• Five spare receivers.

(7)

Clock Generator

(a)

The clocks for the various processors are generated by a Cypress Semiconductor
programmable clock generator integrated circuit. The clock generator derives the
following clocks from a 50.4-MHz clock input from RF CCA:

• 58-MHz clock provided to the MPC8250

• 50-MHz clock provided to the TMS5410 DSP

• 35-MHz clock provided to the TMS6711 DSP

• 25-MHz clock provided to the Ethernet transceiver

• 10.24-MHz clock provided to the audio CODEC.

(8)

Monitoring Circuitry

(a)

The monitoring circuitry consists of voltage level monitoring circuits and a processor
watchdog circuit. The digital processor regulator voltage levels monitored are as follows:

• +12 volts

•

12 volts

• +5 volts

• +3.3 volts

• +2.5 volts

• +1.9 volts

• +1.5 volts

• +1.26 volts.

(b)

The ARINC 429 I/O FPGA provides a supervisory watchdog function used to monitor
the MPC8250 main processor. If the MPC8250 fails to monitor the watchdog register at
10-ms intervals, the MPC8250 is reset by the ARINC 429 I/O FPGA.

EFFECTIVITY

ALL

23-20-59

Page 44

1 Mar 2011