Intel I350-F4 I350F4BLK Manuale Utente
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I350F4BLK
General Features
Features
Benefits
Intel® Ethernet Controller I350
with
PCI Express* V2.1 (5 GT/s) Support
• Industry-leading smallest non-bridged PCIe Gen2 quad-port 1 GbE controller
• Enables customers to take full advantage of 1 GbE by providing maximum bi-directional throughput per port on a single
quad-port adapter
Halogen Free
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(Copper)
• Leadership in an environmentally friendly ecosystem
Low-Profile (Dual and Quad Port Copper; Dual-Port Fiber) and
Standard height (Quad-Port Fiber)
• Enables higher bandwidth and throughput from standard and low-profile PCIe slots and servers
Ethernet Features
Features
Benefits
IEEE* 802.3 auto-negotiation
• Automatic link configuration for speed, duplex, flow control
1Gb/s Ethernet IEEE 802.3, 802.3u, 802.3ab PHY specifications
Compliant
• Robust operation over installed base of Category-5 twisted-pair cabling
Integrated PHY for 10/100/1000 Mb/s for multispeed, full, and
half-duplex
• Smaller footprint and lower power dissipation compared to multiple discreet MAC and PHY
IEEE 802.3x and 802.3z compliant flow control support with
software-controllable Rx thresholds and Tx pause frames
• Local control of network congestion levels
• Frame loss reduced from receive overruns
Automatic cross-over detection function (MDI/MDI-X)
• The PHY automatically detects which application is being used and configures itself accordingly
IEEE 1588 protocol and 802.1AS implementation
• Time-stamping and synchronization of time sensitive applications
• Distribute common time to media devices
Power Management and Efficiency
Features
Benefits
<1W S0-Max (state) 1000BASE-T Active 90oC (mode)
<400mW S0-Typ (state) 100BASE-T Active (mode)
• Controller is designed for low power consumption
IEEE802.3az - Energy Efficient Ethernet (EEE)
• Power consumption of the PHY is reduced by approximately 50% link transitions to low power Idle (LPI) state as defined in
the IEEE802.3az (EEE) standard
DMA Coalescing
• Reduces platform power consumption by coalescing, aligning, and synchronizing DMA
• Enables synchronizing port activity and power management of memory, CPU and RC internal circuitry
Smart Power Down (SPD) at S0 no link / Sx no link
• PHY powers down circuits and clocks that are not required for detection of link activity
Active State Power Management (ASPM) Support
• Optionality Compliance bit to help determine whether to enable ASPM or whether to run ASPM compliance tests to support
entry to L0s
LAN disable function
• Option to disable the LAN Port and/or PCIe Function. Disabling just the PCIe function but keeping the LAN port that resides
on it fully active (for manageability purposes and BMC pass-through traffic).
Full wake up support
• Advanced Power Management (APM) Support (formerly Wake
on LAN)
• Advanced Configuration and Power Interface (ACPI) specification
v2.0c
• Magic Packet* wake-up enable with unique MAC address
• APM - Designed to receive a broadcast or unicast packet with an explicit data pattern (Magic Pack) and assert a signal to
wake up the system
• ACPI - PCIe power management based wake-up that can generate system wake-up events from a number of sources
ACPI register set and power down functionality supporting D0 and
D3 states
• A power-managed link speed control lowers link speed (and power) when highest link performance is not required
MAC Power Management controls
• Power management controls in the MAC the PHY can be entered into a low-power state
Low Power Link Up - Link Speed Control
• Enables a link to come up at the lowest possible speed in cases where power is more important than performance
Power Management Protocol Offload (Proxying)
• Avoid spurious wake up events and reduce system power consumption when the device is in D3 low power state and system
is in S3 or S4 low power states
Latency Tolerance Reporting (LTR)
• Reports service latency requirements for memory reads and writes to the Root Complex for system power management
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