Intel III Xeon 600 MHz 80526KZ600256 Scheda Tecnica
Codici prodotto
80526KZ600256
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache
PROCESSOR FEATURES
51
Table 38. Thermal Sensor Configuration Register
Bit
Name
Reset State
Function
7 (MSB)
RESERVED
0
Reserved for future use.
6
RUN/STOP
0
Standby mode control bit. If high, the device immediately stops
converting, and enters standby mode. If low, the device converts in
either one-shot mode or automatically updates on a timed basis..
5-0
RESERVED
0
Reserved for future use.
5.2.6.5
Conversion Rate Register
The contents of the conversion rate register determine the nominal rate at which analog to digital conversions
happen when the thermal sensor is in auto-convert mode. Table 39 shows the mapping between conversion
rate register values and the conversion rate. As indicated in Table 39, the conversion rate register is set to its
default state of 02h (0.25 Hz nominally) when the thermal sensor is powered up.
happen when the thermal sensor is in auto-convert mode. Table 39 shows the mapping between conversion
rate register values and the conversion rate. As indicated in Table 39, the conversion rate register is set to its
default state of 02h (0.25 Hz nominally) when the thermal sensor is powered up.
There is a ±25% error
tolerance between the conversion rate indicated in the conversion rate register and the actual conversion rate.
Table 39. Thermal Sensor Conversion Rate Register
Register Contents
Conversion Rate (Hz)
00h
0.0625
01h
0.125
02h
0.25
03h
0.5
04h
1
05h
2
06h
4
07h
8
08h to FFh
Reserved for future use
5.2.7
SMBus Device Addressing
Of the addresses broadcast across the SMBus, the memory components claim those of the form
“1010XXYZb”. The “XX” and “Y” bits are used to enable the devices on the cartridge at adjacent addresses.
The Y bit is hard-wired on the cartridge to V SS (‘0’) for the Scratch EEPROM and pulled to VCC_SMB (‘1’) for
the processor Information ROM. The “XX” bits are defined by the processor slot via the SA0 and SA1 pins on
the SC330 connector. These address pins are pulled down (1K ohm) to ensure that the memory components
are in a known state in systems that do not support the SMBus, or only support a partial implementation. The
“Z” bit is the read/write bit for the serial bus transaction.
“1010XXYZb”. The “XX” and “Y” bits are used to enable the devices on the cartridge at adjacent addresses.
The Y bit is hard-wired on the cartridge to V SS (‘0’) for the Scratch EEPROM and pulled to VCC_SMB (‘1’) for
the processor Information ROM. The “XX” bits are defined by the processor slot via the SA0 and SA1 pins on
the SC330 connector. These address pins are pulled down (1K ohm) to ensure that the memory components
are in a known state in systems that do not support the SMBus, or only support a partial implementation. The
“Z” bit is the read/write bit for the serial bus transaction.
The thermal sensor internally decodes 1 of 3 upper address patterns from the bus of the form “0011XXXZb”,
“1001XXXZb” or “0101XXXZb”. The device’s addressing, as implemented, uses SA2 and SA1 and includes a
Hi-Z state for the SA2 address pin. Therefore the thermal sensor supports 6 unique resulting address ranges.
To set the Hi-Z state for SA2, the pin must be left floating. The system should drive SA1 and SA0, and will be
pulled low (if not driven) by the 10K ohm pull-down resistor on the processor substrate. Attempting to drive
either of these signals to a Hi-Z state would cause ambiguity in the memory device address decode, possibly
resulting in the devices not responding, thus timing out or hanging the SMBus. As before, the “Z” bit is the
read/write bit for the serial bus transaction.
“1001XXXZb” or “0101XXXZb”. The device’s addressing, as implemented, uses SA2 and SA1 and includes a
Hi-Z state for the SA2 address pin. Therefore the thermal sensor supports 6 unique resulting address ranges.
To set the Hi-Z state for SA2, the pin must be left floating. The system should drive SA1 and SA0, and will be
pulled low (if not driven) by the 10K ohm pull-down resistor on the processor substrate. Attempting to drive
either of these signals to a Hi-Z state would cause ambiguity in the memory device address decode, possibly
resulting in the devices not responding, thus timing out or hanging the SMBus. As before, the “Z” bit is the
read/write bit for the serial bus transaction.
Note that addresses of the form “0000XXXXb” are reserved and should not be generated by an SMBus
master.
master.