Intel 1.40 GHz YA80543KC0174M Manuale Utente
Codici prodotto
YA80543KC0174M
Datasheet
105
Signals Reference
A.1.64
THRMALERT# (O)
THRMALERT# is asserted when the measured temperature from the processor thermal diode
equals or exceeds the temperature threshold data programmed in the high-temp (THIGH) or low-
temp (TLOW) registers on the sensor. This signal can be used by the platform to implement
thermal regulation features.
equals or exceeds the temperature threshold data programmed in the high-temp (THIGH) or low-
temp (TLOW) registers on the sensor. This signal can be used by the platform to implement
thermal regulation features.
A.1.65
TMS (I)
The Test Mode Select (TMS) signal is an IEEE 1149.1 compliant TAP specification support signal
used by debug tools.
used by debug tools.
A.1.66
TND# (I/O)
The TLB Purge Not Done (TND#) signal is asserted to delay completion of a TLB Purge
instruction, even after the TLB Purge transaction completes on the system bus.
instruction, even after the TLB Purge transaction completes on the system bus.
A.1.67
TRDY# (I)
The Target Ready (TRDY#) signal is asserted by the target to indicate that it is ready to receive a
write or implicit writeback data transfer.
write or implicit writeback data transfer.
A.1.68
TRST# (I)
The TAP Reset (TRST#) signal is an IEEE 1149.1 compliant TAP support signal used by debug
tools.
tools.
A.1.69
WSNP# (I/O)
The Write Snoop (WSNP#) signal indicates that snooping agents will snoop the memory write
transaction
transaction
A.2
Signal Summaries
list attributes of the Itanium 2 processor output, input, and I/O
signals.
Table A-12. Output Signals (Sheet 1 of 2)
Name
Active Level
Clock
Signal Group
CPUPRES#
Low
—
Platform
DBSY_C1#
Low
BCLKp
Data
DBSY_C2#
Low
BCLKp
Data
DRDY_C1#
Low
BCLKp
Data
DRDY_C2#
Low
BCLKp
Data
FERR#
Low
Asynchronous
PC Compatibility,
IERR Mode