Intel 4 515/515J JM80547PE0771M Manuale Utente

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Due to the voltage levels supported by other components in the Test Access Port (TAP) logic, it is 
recommended that the Pentium 4 processor in the 775-land package be first in the TAP chain and 
followed by any other components within the system. A translation buffer should be used to 
connect to the rest of the chain unless one of the other components is capable of accepting an input 
of the appropriate voltage level. Similar considerations must be made for TCK, TMS, TRST#, TDI, 
and TDO. Two copies of each signal may be required, with each driving a different voltage level.

The BSEL[2:0] signals are used to select the frequency of the processor input clock (BCLK[1:0]). 

 defines the possible combinations of the signals and the frequency associated with each 

combination. The required frequency is determined by the processor, chipset, and clock 
synthesizer. All agents must operate at the same frequency. 

The Pentium 4 processor in the 775-land package currently operates at a 533 MHz or 800 MHz 
FSB frequency (selected by a 133 MHz or 200 MHz BCLK[1:0] frequency). Individual processors 
will only operate at their specified FSB frequency.

For more information about these signals, refer to 

L

L

L

RESERVED

L

L

H

133 MHz

L

H

H

RESERVED

L

H

L

200 MHz

H

L

L

RESERVED

H

L

H

RESERVED

H

H

H

RESERVED

H

H

L

RESERVED