Intel Z520PT CH80566EE014DT Scheda Tecnica
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CH80566EE014DT
Thermal Specifications and Design Considerations
Datasheet
71
over TM2 is enabled in MSRs using BIOS and TM2 is not sufficient to cool the
processor below the maximum operating temperature, then TM1 will also activate to
help cool down the processor.
If a processor load based Enhanced Intel SpeedStep Technology transition (through
MSR write) is initiated when a TM2 period is active, there are two possible results:
•
If the processor load based Enhanced Intel SpeedStep Technology transition
target frequency is higher than the TM2 transition based target frequency, the
processor load-based transition will be deferred until the TM2 event has been
completed.
•
If the processor load-based Enhanced Intel SpeedStep Technology transition
target frequency is lower than the TM2 transition based target frequency, the
processor will transition to the processor load-based Enhanced Intel SpeedStep
Technology target frequency point.
The TCC may also be activated using on-demand mode. If bit 4 of the ACPI Intel
Thermal Monitor control register is written to a 1, the TCC will be activated
immediately independent of the processor temperature. When using on-demand mode
to activate the TCC, the duty cycle of the clock modulation is programmable using bits
3:1 of the same ACPI Intel Thermal Monitor control register. In automatic mode, the
duty cycle is fixed at 50% on, 50% off, however in on-demand mode, the duty cycle
can be programmed from 12.5% on/ 87.5% off, to 87.5% on/12.5% off in 12.5%
increments. On-demand mode may be used at the same time automatic mode is
enabled—however, if the system tries to enable the TCC using on-demand mode at
the same time automatic mode is enabled and a high temperature condition exists,
automatic mode will take precedence.
An external signal, PROCHOT# (processor hot) is asserted when the processor detects
that its temperature is above the thermal trip point. Bus snooping and interrupt
latching are also active while the TCC is active.
Besides the thermal sensor and thermal control circuit, the Intel Thermal Monitor also
includes one ACPI register, one performance counter register, three MSR, and one I/O
pin (PROCHOT#). All are available to monitor and control the state of the Intel
Thermal Monitor feature. The Intel Thermal Monitor can be configured to generate an
interrupt upon the assertion or de-assertion of PROCHOT#.
PROCHOT# will not be asserted when the processor is in the Stop Grant, Sleep, Deep
Sleep, and Deeper Sleep low power states—hence, the thermal diode reading must be
used as a safeguard to maintain the processor junction temperature within maximum
specification. If the platform thermal solution is not able to maintain the processor
junction temperature within the maximum specification, the system must initiate an
orderly shutdown to prevent damage. If the processor enters one of the above low
power states with PROCHOT# already asserted, PROCHOT# will remain asserted until
the processor exits the low power state and the processor junction temperature drops
below the thermal trip point.
If Intel Thermal Monitor automatic mode is disabled, the processor will operate out of
specification. Regardless of enabling the automatic or on-demand modes, in the event
of a catastrophic cooling failure, the processor will automatically shut down when the
silicon has reached a temperature of approximately 120 °C. At this point the
THERMTRIP# signal will go active. THERMTRIP# activation is independent of processor
activity and does not generate any bus cycles. When THERMTRIP# is asserted, the