Intel i7-3920XM Extreme AW8063801009607 Manuale Utente
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AW8063801009607
Processor Configuration Registers
186
Datasheet, Volume 2
2.10.31 MA—Message Address Register
6:4
RW
000b
Uncore
Multiple Message Enable (MME)
System software programs this field to indicate the actual
System software programs this field to indicate the actual
number of messages allocated to this device. This number will be
equal to or less than the number actually requested.
The encoding is the same as for the MMC field below.
The encoding is the same as for the MMC field below.
3:1
RO
000b
Uncore
Multiple Message Capable (MMC)
System software reads this field to determine the number of
System software reads this field to determine the number of
messages being requested by this device.
000 = 1
All of the following are reserved in this implementation:
001 = 2
010 = 4
011 = 8
100 = 16
101 = 32
110 = Reserved
111 = Reserved
000 = 1
All of the following are reserved in this implementation:
001 = 2
010 = 4
011 = 8
100 = 16
101 = 32
110 = Reserved
111 = Reserved
0
RW
0b
Uncore
MSI Enable (MSIEN)
This bit controls the ability of this device to generate MSIs.
0 = MSI will not be generated.
1 = MSI will be generated when we receive PME messages. INTA
This bit controls the ability of this device to generate MSIs.
0 = MSI will not be generated.
1 = MSI will be generated when we receive PME messages. INTA
will not be generated and INTA Status (PCISTS1[3]) will not
be set.
B/D/F/Type:
0/6/0/PCI
Address Offset:
94-97h
Reset Value:
00000000h
Access:
RW, RO
Size:
32 bits
Bit
Access
Reset
Value
RST/
PWR
Description
31:2
RW
00000000h
Uncore
Message Address (MA)
Used by system software to assign an MSI address to the device.
Used by system software to assign an MSI address to the device.
The device handles an MSI by writing the padded contents of the
MD register to this address.
1:0
RO
00b
Uncore
Force DWord Align (FDWA)
Hardwired to 0 so that addresses assigned by system software
Hardwired to 0 so that addresses assigned by system software
are always aligned on a DWord address boundary.
B/D/F/Type:
0/6/0/PCI
Address Offset:
92–93h
Reset Value:
0000h
Access:
RO, RW
Size:
16 bits
BIOS Optimal Default
00h
Bit
Access
Reset
Value
RST/
PWR
Description