Intel G640 CM8062307260314 Manuale Utente
Codici prodotto
CM8062307260314
Interfaces
24
Datasheet, Volume 1
2.2
PCI Express* Interface
This section describes the PCI Express interface capabilities of the processor. See the
PCI Express Base Specification for details of PCI Express.
PCI Express Base Specification for details of PCI Express.
The number of PCI Express controllers available is dependent on the platform:
• Processor with desktop Intel 5 Series Chipset: 1 x 16 PCI Express Graphics is
supported.
• Processor with Intel 5 Series Chipset P55 and P57 SKUs: 2 x 8 PCI Express
Graphics is supported.
• Processor with workstation Intel 3400 Series Chipset: 1 x 16 PCI Express Graphics
or 2 x 8 PCI Express is supported (1 x8 primary port for graphics or I/O; 1 x 8
secondary port for I/O only).
secondary port for I/O only).
It defines the PCI Express port that is used as the external graphics attach. The port
may also be referred to as PEG (or PEG0) and PCI Express Graphics Port.
may also be referred to as PEG (or PEG0) and PCI Express Graphics Port.
2.2.1
PCI Express* Architecture
Compatibility with the PCI addressing model is maintained to ensure that all existing
applications and drivers operate unchanged.
applications and drivers operate unchanged.
The PCI Express configuration uses standard mechanisms as defined in the PCI Plug-
and-Play specification. The initial recovered clock speed of 1.25 GHz results in
2.5 Gb/s/direction which provides a 250-MB/s communications channel in each
direction (500 MB/s total). That is close to twice the data rate of classic PCI. The fact
that 8b/10b encoding is used accounts for the 250 MB/s where quick calculations would
imply 300 MB/s. The PCI Express ports support 5.0 GT/s speed as well. Operating at
5.0 GT/s results in twice as much bandwidth per lane as compared to 2.5 GT/s
operation.
and-Play specification. The initial recovered clock speed of 1.25 GHz results in
2.5 Gb/s/direction which provides a 250-MB/s communications channel in each
direction (500 MB/s total). That is close to twice the data rate of classic PCI. The fact
that 8b/10b encoding is used accounts for the 250 MB/s where quick calculations would
imply 300 MB/s. The PCI Express ports support 5.0 GT/s speed as well. Operating at
5.0 GT/s results in twice as much bandwidth per lane as compared to 2.5 GT/s
operation.
The PCI Express architecture is specified in three layers: Transaction Layer, Data Link
Layer, and Physical Layer. The partitioning in the component is not necessarily along
these same boundaries. Refer to
Layer, and Physical Layer. The partitioning in the component is not necessarily along
these same boundaries. Refer to
for the PCI Express Layering Diagram.
Figure 2-3. PCI Express* Layering Diagram