Intel i5-2540M FF8062700839209 Manuale Utente
Codici prodotto
FF8062700839209
Datasheet
71
Signal Description
6.2
Memory Reference and Compensation
SB_DQS[7:0]
Data Strobes: SB_DQS[7:0] and its
complement signal group make up a
differential strobe pair. The data is captured
at the crossing point of SB_DQS[7:0] and its
SB_DQS#[7:0] during read and write
transactions.
complement signal group make up a
differential strobe pair. The data is captured
at the crossing point of SB_DQS[7:0] and its
SB_DQS#[7:0] during read and write
transactions.
I/O
DDR3
SB_DQS#[7:0]
Data Strobe Complements: These are the
complementary strobe signals.
complementary strobe signals.
I/O
DDR3
SB_DQ[63:0]
Data Bus: Channel B data signal interface to
the SDRAM data bus.
the SDRAM data bus.
I/O
DDR3
SB_MA[15:0]
Memory Address: These signals are used to
provide the multiplexed row and column
address to the SDRAM.
provide the multiplexed row and column
address to the SDRAM.
O
DDR3
SB_CK[1:0]
SDRAM Differential Clock: Channel B
SDRAM Differential clock signal pair. The
crossing of the positive edge of SB_CK and
the negative edge of its complement
SB_CK# are used to sample the command
and control signals on the SDRAM.
SDRAM Differential clock signal pair. The
crossing of the positive edge of SB_CK and
the negative edge of its complement
SB_CK# are used to sample the command
and control signals on the SDRAM.
O
DDR3
SB_CK#[1:0]
SDRAM Inverted Differential Clock:
Channel B SDRAM Differential clock signal-
pair complement.
Channel B SDRAM Differential clock signal-
pair complement.
O
DDR3
SB_CKE[1:0]
Clock Enable: (1 per rank) Used to:
- Initialize the SDRAMs during power-up.
- Power-down SDRAM ranks.
- Place all SDRAM ranks into and out of self-
refresh during STR.
- Initialize the SDRAMs during power-up.
- Power-down SDRAM ranks.
- Place all SDRAM ranks into and out of self-
refresh during STR.
O
DDR3
SB_CS#[1:0]
Chip Select: (1 per rank) Used to select
particular SDRAM components during the
active state. There is one Chip Select for
each SDRAM rank.
particular SDRAM components during the
active state. There is one Chip Select for
each SDRAM rank.
O
DDR3
SB_ODT[1:0]
On Die Termination: Active Termination
Control.
Control.
O
DDR3
Table 27.
Memory Reference and Compensation
Signal Name
Description
Direction/Buffer
Type
SA_DIMM_VREFDQ
SB_DIMM_VREFDQ
SB_DIMM_VREFDQ
Memory Channel A/B DIMM DQ
Reference Voltage
Reference Voltage
O
A
SM_RCOMP[2:0]
System Memory Impedance
Compensation
Compensation
I
A
Table 26.
Memory Channel B (Sheet 2 of 2)
Signal Name
Description
Direction/Buffer
Type