Samsung MZMPC128HBFU-00000 Manuale Utente

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        datasheet
SSD
  Rev. 1.0
MZMPC032HBCD-00000
MZMPC064HBDR-00000
MZMPC128HBFU-00000
MZMPC256HBGJ-00000
6.5 Features Register
This register is command specific. This is used with the Set Features command, S.M.A.R.T. Function Set command.
6.6 Cylinder High (LBA High) Register
This register contains Bits 16-23. At the end of the command, this register is updated to reflect the current LBA Bits 16-23.
6.7 Cylinder Low (LBA Mid) Register
This register contains Bits 8-15. At the end of the command, this register is updated to reflect the current LBA Bits 8-15.
When 48-bit addressing commands are used, the "most recently written" content contains LBA Bits 8-15, and the "previous content" contains Bits 32-39
6.8 Sector Number (LBA low) Register
This register contains Bits 0-7. At the end of the command, this register is updated to reflect the current LBA Bits 0-7.
When 48-bit commands are used, the "most recently written" content contains LBA Bits 0-7, and the "previous content" contains Bits 24-31.
6.9 Sector Count Register
This register contains the number of sectors of data requested to be transferred on a read or write operation between the host and the device. If the value 
in the register is set to 0, a count of 256 sectors (in 28-bit addressing) or 65,536 sectors (in 48-bit addressing) is specified.
If the register is zero at command completion, the command was successful. If not successfully completed, the register contains the number of sectors 
which need to be transferred in order to complete the request.
The contents of the register are defined otherwise on some commands. These definitions are given in the command descriptions.
6.10
 
Status Register
This register contains the device status. The contents of this register are updated whenever an error occurs and at the completion of each command.
If the host reads this register when an interrupt is pending, it is considered to be the interrupt acknowledge. Any pending interrupt is cleared whenever this 
register is read.
If BSY=1, no other bits in the register are valid. And read/write operations of any other register are negated in order to avoid the returning of the contesnts 
of this register instead of the other registers’ contents.
6.10.1 Field / bit description
• BSY : Busy. BSY=1 whenever the device is accessing the registers. The host should not read or write any registers when BSY=1. If the host reads any register when BSY=1, 
the contents of the Status Register will be returned.
• DRDY : Device Ready. RDY=1 indicates that the device is capable of responding to a command. RDY will be set to 0 during power on until the device is ready to accept a 
command.
• DF : Device Fault. DF=1 indicates that the device has detected a write fault condition. DF is set to 0 after the Status Register is read by the host.
• DSC : Device Seek Complete. DSC=1 indicates that a seek has completed and the device head is settled over a track. DSC is set to 0 by the device just before a seek begins. 
When an error occurs, this bit is not changed until the Status Register is read by the
host, at which time the bit again indicates the current seek complete status.
When the device enters into or is in Standby mode or Sleep mode, this bit is set by device in spite of not spinning up.
• DRQ : Data Request. DRQ=1 indicates that the device is ready to transfer a word or byte of data between the host and the device. The host should not write the Command 
register when DRQ=1.
• CORR : Corrected Data. Always 0.
• IDX : Index. IDX=1 once per revolution. Since IDX=1 only for a very short time during each revoltion, the host may not see it set to
1 even if the host is reading the Status Register continuously. Therefore the host should not attempt to use IDX for timing purposes.
• ERR : ERR=1 indicates that an error occurred during execution of the previous command. The Error Register should be read to determine the error type. The device sets 
ERR=0 when the next command is received from the host.
7
6
5
4
3
2
1
0
BSY
DRDY
DF
DSC
DRQ
CORR
IDX
ERR