Intel G645 CM8062301262601 Manuale Utente
Codici prodotto
CM8062301262601
Datasheet, Volume 2
229
Processor Configuration Registers
24
WO
0b
Uncore
Set Interrupt Remap Table Pointer (SIRTP)
This field is valid only for implementations supporting interrupt-
This field is valid only for implementations supporting interrupt-
remapping.
Software sets this field to set/update the interrupt remapping table
Software sets this field to set/update the interrupt remapping table
pointer used by hardware. The interrupt remapping table pointer is
specified through the Interrupt Remapping Table Address
(IRTA_REG) register.
Hardware reports the status of the 'Set Interrupt Remap Table
Hardware reports the status of the 'Set Interrupt Remap Table
Pointer' operation through the IRTPS field in the Global Status
register.
The 'Set Interrupt Remap Table Pointer' operation must be
The 'Set Interrupt Remap Table Pointer' operation must be
performed before enabling or re-enabling (after disabling)
interrupt-remapping hardware through the IRE field.
After a 'Set Interrupt Remap Table Pointer' operation, software
After a 'Set Interrupt Remap Table Pointer' operation, software
must globally invalidate the interrupt entry cache. This is required
to ensure hardware uses only the interrupt-remapping entries
referenced by the new interrupt remap table pointer, and not any
stale cached entries.
While interrupt remapping is active, software may update the
While interrupt remapping is active, software may update the
interrupt remapping table pointer through this field. However, to
ensure valid in-flight interrupt requests are deterministically
remapped, software must ensure that the structures referenced by
the new interrupt remap table pointer are programmed to provide
the same remapping results as the structures referenced by the
previous interrupt remap table pointer.
Clearing this bit has no effect. The value returned on a read of this
Clearing this bit has no effect. The value returned on a read of this
field is undefined.
23
WO
0b
Uncore
Compatibility Format Interrupt (CFI)
This field is valid only for Intel 64 implementations supporting
This field is valid only for Intel 64 implementations supporting
interrupt-remapping.
Software writes to this field to enable or disable Compatibility
Software writes to this field to enable or disable Compatibility
Format interrupts on Intel 64 platforms. The value in this field is
effective only when interrupt-remapping is enabled and Extended
Interrupt Mode (x2APIC mode) is not enabled.
0 = Block Compatibility format interrupts.
0 = Block Compatibility format interrupts.
1 = Process Compatibility format interrupts as pass-through
(bypass interrupt remapping).
Hardware reports the status of updating this field through the CFIS
field in the Global Status register.
The value returned on a read of this field is undefined.
The value returned on a read of this field is undefined.
22:0
RO
0h
Reserved
B/D/F/Type:
0/0/0/GFXVTBAR
Address Offset:
18–1Bh
Reset Value:
0000_0000h
Access:
RO, WO
Size:
32 bits
BIOS Optimal Default
000000h
Bit
Attr
Reset
Value
RST/
PWR
Description