Intel E7-8891 v2 CM8063601377422 Manuale Utente

128

Intel

®

 Xeon

® 

Processor E7-2800/4800/8800 v2 Product Family

Datasheet Volume Two: Functional Description, February 2014

17:17

WO

0x0

Counter Reset (counterreset):

When this bit is set, the corresponding counter will be reset to 0. This allows 

for a quick reset of the counter when changing event encodings.

16:16

WO

0x0

Queue Occupancy Reset (queueoccupancyreset):

This write only bit causes the queue occupancy counter of the PerfMon 

counter for which this Perf event select register is associated to be cleared 

to all zeroes when a ‘1’ is written to it. No action is taken when a ‘0’ is 

written. Note: Since the queue occupancy counters never drop below zero, 

it is possible for the counters to 'catch up' with the real occupancy of the 

queue in question when the real occupancy drop to zero.

15:8

RW_V

0x0

Unit Mask (unitmask):

This mask selects the subevents to be selected for creation of the event. 

The selected subevents are bitwise OR-ed together to create event. At least 

one subevent must be selected otherwise the PerfMon event signals will not 

ever get asserted. Events with no subevents listed effectively have only one 

subevent = event -1 -- bit 8 must be set to 1 in this case.

7:0

RW_V

0x0

Event Select (eventselect):

This field is used to decode the PerfMon event which is selected. 

31:18

RV

-

Reserved.

17:17

RW_L

0x1

Overflow Enable (overflowenable):

This bit controls the behavior of counters when they overflow. When set, the 

system will trigger the overflow handling process throughout the rest of the 

uncore, potentially triggering a PMI and freezing counters. When it is not set, 

the counters will simply wrap around and continue to count.

16:16

RW_L

0x1

Freeze Enable (freezeenable):

This bit controls what the counters in the unit will do when they receive a freeze 

signal. When set, the counters will be allowed to freeze. When not set, the 

counters will ignore the freeze signal.

15:9

RV

-

Reserved.

8:8

RW_V

0x0

Freeze Counters (freezecounters):

This bit is written to when the counters should be frozen. If this bit is written to 

and freeze is enabled, the counters in the unit will stop counting.

7:2

RV

-

Reserved.

1:1

WO

0x0

Reset Counters (resetcounters):

When this bit is written to, the counters data fields will be reset. The 

configuration values will not be reset.