Intel E7-8891 v2 CM8063601377422 Manuale Utente
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CM8063601377422
Intel
®
Xeon
®
Processor E7-2800/4800/8800 v2 Product Family
275
Datasheet Volume Two: Functional Description, February 2014
Integrated I/O (IIO) Configuration Registers
14.2.103 XPCOREDMASK
XP Correctable Error Detect Mask
This register masks other correctable errors from causing the associated
XPCORERRSTS status bit to be set.
XPCORERRSTS status bit to be set.
14.2.104 XPGLBERRSTS
XP Global Error Status
This register captures a concise summary of the error logging in AER registers so that
sideband system management software can view the errors independent of the main
OS that might be controlling the AER errors.
sideband system management software can view the errors independent of the main
OS that might be controlling the AER errors.
14.2.105 XPGLBERRPTR
XP Global Error Pointer
Type:
CFG
PortID:
N/A
Bus:
0
Device:
0Function:0
Bus:
0
Device:
2Function:0-3
Bus:
0
Device:
3Function:0-3
Offset:
0x228
Bit
Attr
Default
Description
31:1
RV
-
Reserved.
0:0
RWS
0x0
pci_link_bandwidth_changed_detect_mask:
Type:
CFG
PortID:
N/A
Bus:
0
Device:
0Function:0
Bus:
0
Device:
2Function:0-3
Bus:
0
Device:
3Function:0-3
Offset:
0x230
Bit
Attr
Default
Description
15:3
RV
-
Reserved.
2:2
RW1CS
0x0
pcie_aer_correctable_error:
A PCIe* correctable error (ERR_COR message received from externally or
through a virtual ERR_COR message generated internally) was detected
anew. Note that if that error was masked in the PCIe* AER, it is not reported
in this field. Software clears this bit by writing a 1 and at that stage, only
‘subsequent’ PCIe* unmasked correctable errors will set this bit.Concep-
tually, per the flow of PCI Express Base Spec 2.0 defined Error message
control, this bit is set by the ERR_COR message that is enabled to cause a
System Error notification.
1:1
RW1CS
0x0
pcie_aer_non_fatal_error:
A PCIe* nonfatal error (ERR_NONFATAL message received from externally or
through a virtual ERR_NONFATAL message generated internally) was
detected anew. Note that if that error was masked in the PCIe* AER, it is not
reported in this field. Software clears this bit by writing a 1 and at that stage
only ‘subsequent’ PCIe* unmasked nonfatal errors will set this bit again.
0:0
RW1CS
0x0
pcie_aer_fatal_error:
A PCIe* fatal error (ERR_FATAL message received from externally or through
a virtual ERR_FATAL message generated internally) was detected anew. Note
that if that error was masked in the PCIe* AER, it is not reported in this field.
Software clears this bit by writing a 1 and at that stage, only ‘subsequent’
PCIe* unmasked fatal errors will set this bit.