Intel E7-8891 v2 CM8063601377422 Manuale Utente

Intel

®

 Xeon

® 

Processor E7-2800/4800/8800 v2 Product Family

345

Datasheet Volume Two: Functional Description, February 2014

Channel Completion Address 0 Register.

This register specifies the address where the DMA channel writes the completion status 
upon completion or an error condition that is, it writes the contents of the CHANSTS 
register to the destination as pointed by the CHANCMP register.

Channel Completion Address 1 Register.

This register specifies the address where the DMA channel writes the completion status 
upon completion or an error condition that is, it writes the contents of the CHANSTS 
register to the destination as pointed by the CHANCMP register.

The Channel Error Register records the error conditions occurring within a given DMA 
channel.

31:3

RW_L

0x0

chcmpladdr_lo:

This 64-bit field specifies the address where the DMA engine writes the 

completion status (CHANSTS). This address can fall within system memory or 

memory-mapped I/O space but should be 8-byte aligned.This register is RW 

if CHANCNT register is 1 otherwise this register is RO.

2:0

RV

-

Reserved. 

31:0

RW_L

0x0

chcmpladdr_hi:

This 64-bit field specifies the address where the DMA engine writes the 

completion status (CHANSTS). This address can fall within system memory or 

memory-mapped I/O space but should be 8-byte aligned.This register is RW 

if CHANCNT register is 1 otherwise this register is RO.

31:19

RV

-

Reserved. 

18:18

RW1CS (Function 0-1)
RO (Function 2-7)

0x0

desccnterr:

The hardware sets this bit when it encounters a base 

descriptor that requires an extended descriptor (such as an 

XOR with 8 sources), but DMACount indicates that the Base 

descriptor is the last descriptor that can be processed.