Intel E7-4850 v2 CM8063601272906 Manuale Utente
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CM8063601272906
Integrated I/O (IIO) Configuration Registers
268
Intel
®
Xeon
®
Processor E7-2800/4800/8800 v2 Product Family
Datasheet Volume Two: Functional Description, February 2014
14.2.90 ERRINJHDR
PCI Express Error Injection Capability Header.
14.2.91 ERRINJCON
PCI Express Error Injection Control Register.
Type:
CFG
PortID:
N/A
Bus:
0
Device:
0Function:0
Bus:
0
Device:
2Function:0-3
Bus:
0
Device:
3Function:0-3
Offset:
0x1d4
Bit
Attr
Default
Description
31:20
RO
0xa
vseclen:
Vendor Specific Capability Length
Indicates the length of the capability structure, including header bytes.
Indicates the length of the capability structure, including header bytes.
19:16
RO
0x1
vsecrev:
Vendor Specific Capability Revision
Set to 1h for this version of the WHEA Error Injection logic.
Set to 1h for this version of the WHEA Error Injection logic.
15:0
RO
0x3
vsecid:
Vendor Specific ID
Assigned for WHEA Error Injection
Assigned for WHEA Error Injection
Type:
CFG
PortID:
N/A
Bus:
0
Device:
0Function:0
Bus:
0
Device:
2Function:0-3
Bus:
0
Device:
3Function:0-3
Offset:
0x1d8
Bit
Attr
Default
Description
15:3
RV
-
Reserved.
2:2
RW
0x0
cause_ctoerr:
Cause a Completion Timeout Error
When this bit is written to transition from 0 to 1, one and only one error
When this bit is written to transition from 0 to 1, one and only one error
assertion pulse is produced on the error source signal for the given port. This
error will appear equivalent to an actual error assertion because this event is
OR’d into the existing error reporting structure. To log another error, this bit
must be cleared first, before setting again. Leaving this bit in a 1 state does
not produce a persistent error condition.
Note:
This bit is used for an uncorrectable error test
This bit must be cleared by software before creating another event.
This bit is disabled by bit 0 of this register
This bit is used for an uncorrectable error test
This bit must be cleared by software before creating another event.
This bit is disabled by bit 0 of this register