Intel E7-8880L v2 CM8063601275812 Manuale Utente
Codici prodotto
CM8063601275812
Integrated I/O (IIO) Configuration Registers
338
Intel
®
Xeon
®
Processor E7-2800/4800/8800 v2 Product Family
Datasheet Volume Two: Functional Description, February 2014
9:9
RO_V (Function 0-1)
RO (Function 2-7)
RO (Function 2-7)
0x0
xor_raid6:
If set, specifies XOR with Galios Field Multiply Parity and Quotient
opcodes for RAID5 and RAID6 are supported. The opcodes are:
0x89 - XOR with Galios Field Multiply Generation
0x8A - XOR with Galios Field Multiply Validate
0x8B - XOR with Galios Field Multiply Update Generation
0x89 - XOR with Galios Field Multiply Generation
0x8A - XOR with Galios Field Multiply Validate
0x8B - XOR with Galios Field Multiply Update Generation
Notes:
When this bit is zero, the DMA engine will halt if it encounters a
When this bit is zero, the DMA engine will halt if it encounters a
descriptor with these opcodes.
8:8
RO
0x0
xor_raid5:
If set, specifies XOR without Galios Field Multiply parity only
opcodes for RAID5 are supported. The opcodes are:
0x87 - XOR Generation
0x88 - XOR Validate
0x87 - XOR Generation
0x88 - XOR Validate
Notes:
When this bit is zero, the DMA engine will halt if it encounters a
When this bit is zero, the DMA engine will halt if it encounters a
descriptor with these opcodes.
7:7
RO
0x1
extended_apic_id:
Set if 32b APIC IDs are supported.
1: 32b APIC IDs supported
0: 8b APIC IDs supported
0: 8b APIC IDs supported
6:6
RO
0x1
block_fill:
If set, specifies the Block Fill opcode is supported. The opcode is:
0x01 - Block Fill
0x01 - Block Fill
Notes:
When this bit is zero, the DMA engine will abort if it encounters a
When this bit is zero, the DMA engine will abort if it encounters a
descriptor with these opcodes.
5:5
RO
0x1
move_crc:
If set, specifies Move and CRC opcodes are supported. The
opcodes are:
0x41 - Move and Generate CRC-32
0x42 - Move and Test CRC-32
0x43 - Move and Store CRC-32
0x41 - Move and Generate CRC-32
0x42 - Move and Test CRC-32
0x43 - Move and Store CRC-32
Notes:
When this bit is zero, the DMA engine will abort if it encounters a
When this bit is zero, the DMA engine will abort if it encounters a
descriptor with these opcodes.
4:4
RW_O
0x1
dca:
If set, specifies DMA DCA operations are supported according to
the settings in the descriptors.
Notes:
When this bit is zero, the DMA engine ignores the DCA hints in
When this bit is zero, the DMA engine ignores the DCA hints in
DMA descriptors.
This bit is RW_O to give bios the ability to turn off DCA operation
This bit is RW_O to give bios the ability to turn off DCA operation
from Intel® Quick Data DMA.
Type:
MEM
PortID:
8’h7e
Bus:
0
Device:
4Function:0-7
Offset:
0x10
Bit
Attr
Default
Description