Intel E7-4830 v2 CM8063601374506 Manuale Utente

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CM8063601374506

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Intel® Xeon® Processor E7-2800/4800/8800 v2 Product Family

Datasheet Volume Two: Functional Description, February 2014

iMC Interface ....................................................................................................37
4.6.1

HA to MC Interface .................................................................................37

Target Address Decode (TAD)...................................................................37

iMC Functional Description.......................................................................................39
5.1

Overview ..........................................................................................................39

Operation .........................................................................................................40
5.2.1

Overview ...............................................................................................40

Logical and Physical Channels...................................................................41

Lockstep................................................................................................41

Independent Channel Mode......................................................................41

Memory Address Decode.....................................................................................41
5.3.1

Summary of Address Translation ..............................................................42

DRAM Maintenance Operations .................................................................42

Refresh .................................................................................................42

IIO Functional Description .......................................................................................45
6.1

Integrated I/O Module Overview ..........................................................................45
6.1.1

PCI Express* Features.............................................................................45

Direct Media Interface (DMI2) Features .....................................................46

PCIe* 3.0 ..............................................................................................46

I/O Acceleration Technology (Intel

I/OAT) 4....................................46

Virtualization Technology (Intel

VT) for Directed I/O

®

VT-d 2) Features..........................................................................46

Power Management Support Features........................................................46

Security Features....................................................................................46

PECI and JTAG ..................................................................................................47
6.2.1

PECI .....................................................................................................47

JTAG.....................................................................................................47

PCI Express and DMI Interfaces...........................................................................47
6.3.1

PCI Express ...........................................................................................47

Speed Support .......................................................................................47

PCI Express Link Characteristics - Bifurcation, Link

Training, Downgrading and Lane Reversal Support ......................................47

Technologies Supported over PCI Express ..................................................49

32/64 Bit Addressing...............................................................................49

Direct Media Interface (DMI) ....................................................................49

Power Management............................................................................................49

Intel Virtualization Technology.............................................................................49

Reliability, Availability, Serviceability, and Manageability ........................................51
7.1

RASM Overview .................................................................................................51
7.1.1

Error Sources .........................................................................................52

Error Classification ..................................................................................52

RASM Feature Summary ..........................................................................53

Error Detection and Correction ............................................................................54

Error Reporting via Machine Check Architecture .....................................................54
7.3.1

Viral Alert ..............................................................................................54

Memory RAS .....................................................................................................55
7.4.1

Features and Capabilities .........................................................................55

Write Data Buffer Parity...........................................................................55

Mirroring ...............................................................................................55

Sparing and Scrubber..............................................................................55

Single Device Data Correction (SDDC) .......................................................56

Double Device Data Correction (DDDC)......................................................56

+1 Bit Correction Beyond Device Correction ...............................................56

PECI Write Accessibility to iMC Registers ....................................................56

iMC Error Handling..................................................................................56