Intel E7-4890 v2 CM8063601272412 Manuale Utente
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CM8063601272412
Intel
®
Xeon
®
Processor E7-2800/4800/8800 v2 Product Family
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Datasheet Volume Two: Functional Description, February 2014
Reliability, Availability, Serviceability, and Manageability
The expectation is that a system cold reset must be performed when a fatal error/viral
condition is detected.
condition is detected.
7.4
Memory RAS
This chapter describes the Intel Xeon processor E7 v2 product family memory
RAS features.
RAS features.
7.4.1
Features and Capabilities
The memory controller implements several RAS features that provide increasing levels
of reliability in exchange for certain system costs.
of reliability in exchange for certain system costs.
7.4.2
Write Data Buffer Parity
The iMC write buffers will store one parity bit per 64 data bits. Parity will be checked
when the data is read out of the buffer to perform a write.
when the data is read out of the buffer to perform a write.
7.4.3
Mirroring
Memory mirroring is the mechanism by which a component of memory is mirrored. In
mirrored mode, typically, when a write is performed to one copy, a write is generated to
the target location as well. This guarantees that the target is always updated with the
latest data from the main copy.
mirrored mode, typically, when a write is performed to one copy, a write is generated to
the target location as well. This guarantees that the target is always updated with the
latest data from the main copy.
7.4.4
Sparing and Scrubber
There is one common hardware engine used for sparing and patrol scrubbing, so only
one such operation can be performed at a time.
one such operation can be performed at a time.
7.4.4.1
Demand and Patrol Scrubbing
Demand scrubbing is the ability to write corrected data back to the memory once a
correctable error is detected on a read transaction. This allows for correction of data in
memory at detect, and decrease the chances of a second error on the same address
accumulating to cause a multi-bit error condition.
correctable error is detected on a read transaction. This allows for correction of data in
memory at detect, and decrease the chances of a second error on the same address
accumulating to cause a multi-bit error condition.
Patrol scrubbing is accomplished using an engine that generates requests to memory
addresses in a stride. The engine will generate a memory request at the pre-
programmed frequency, and the demand scrubbing flow corrects the error, if any. Patrol
scrubbing finds opportunities on idle cycles to scrub the memory and get rid of any
detectable correctable errors.
addresses in a stride. The engine will generate a memory request at the pre-
programmed frequency, and the demand scrubbing flow corrects the error, if any. Patrol
scrubbing finds opportunities on idle cycles to scrub the memory and get rid of any
detectable correctable errors.
7.4.4.1.1
Patrol Scrubbing
Patrol scrubs are intended to ensure that data with a correctable error does not remain
in DRAM long enough to stand a significant chance of further corruption to a
uncorrectable error.
in DRAM long enough to stand a significant chance of further corruption to a
uncorrectable error.
7.4.4.1.2
Demand Scrubbing
Demand scrubbing is an insurance policy for when an error is encountered during a
system read. Demand scrubbing in Intel Xeon processor E7 v2 product family is
handled by the HA.
system read. Demand scrubbing in Intel Xeon processor E7 v2 product family is
handled by the HA.