Intel J1850 FH8065301455200 Manuale Utente

1140

Datasheet

NMI support is enabled by setting the NMI Enable (NMI_EN) bit, at IO Port 70h, Bit 7, 
to 1b. 

Non-Maskable Interrupts (NMIs) can be generated by several sources, as described in 

SERR# goes active 

NOTE: A SERR# is only generated 

internally in the processor)

NSC.SNE

NSC.SNS

All NMI sources may, 

alternatively, generate a SMI 

by setting 

GNMI.NMI2SMIEN=1b 

The processor uses 

GNMI.NMI2SMIST for 

observing SMI status

IOCHK# goes active 

NOTE: A IOCHK# is only generated as a 

SERIRQ# frame 

NSC.INE

NSC.INS

ILB_NMI goes active

NOTE: Active can be defined as being 

on the positive or negative edge 

of the signal using the 

GNMI.GNMIED register bit.

GNMI.GNMIED

GNMI.GNMIS

Software sets the GNMI.NMIN register bit

GNMI.NMIN

GNMI.NMINS