Intel J1750 FH8065301562600 Manuale Utente

Datasheet

1081

This register is a combination of two registers: the interrupt enable register (IER) when 

DLAB=0 and the divisor latch MSB (DLM) register when DLAB=1.

Default: 00h

7:0

00h

RW

register and DLAB=1'b0, it contains the byte received if no FIFO is used, or the oldest 

unread byte with FIFO's. If FIFO buffering is used, each new read action of the register 

will return the next byte, until no more bytes are present. Bit 0 in the LSR line status 

register can be used to check if all received bytes have been read. This bit wil change to 

zero if no more bytes are present. When writing to this register and DLAB=1'b0, it 

is used to buffer outgoing characters. If no FIFO buffering is used, only one character 

can be stored. Otherwise the amount of characters depends on the type of UART. Bit 5 in 

the LSR, line status register can be used to check if new information must be written to 

this register. The value 1'b1 indicates that the register is empty. If FIFO buffering is 

used, more than one character can be written to the transmitter holding register when 

the bit signals an empty state. There is no indication of the amount of bytes currently 

present in the transmitter FIFO. This register is not used to transfer the data directly. 

The byte is first transferred to a shift register where the information is broken in single 

bits which are sent one by one. If DLAB=1'b1, this register is used as DLL (Divisor 

Latch LSB). For generating its timing information, each UART uses an oscillator 

generating a frequency of about 1.8432 MHz. This frequency is divided by 16 to 

generate the time base for communucation. Because of this division, the maximum 

allowed communication speed is 115200 bps. Modern UARTS like the 16550 are capable 

of handling higher input frequencies up to 24 MHz which makes it possible to 

communicate with a maximum speed of 1.5 Mbps. On PC's higher frequencies than the 

1.8432 MHz are rarely seen because this would be software incompatible with the 

original XT configuration. This 115200 bps communication speed is not suitable for all 

applications. To change the communication speed, the frequency can be further 

decreased by dividing it by a programmable value. For very slow communications, this 

value can go beyond 255. Therefore, the divisor is stored in two seperate bytes, the 

divisor latch registers DLL and DLM which contain the least, and most significant byte. 

For error free communication, it is necessary that both the transmitting and receiving 

UART use the same time base. Default values have been defined which are commonly 

used. The table shows the most common values with the appropriate settings of the 

divisor latch bytes. Note that these values only hold for a PC compatible system where a 

clock frequency of 1.8432 MHz is used. Speed(bps) Divisor DLL DLM 

50 2,304 0x00 0x09 300

384 0x80 0x01 

1,200

96 0x60 0x00 2,400

48 0x30 0x00 

4,800

24 0x18 0x00 9,600

12 0x0C 0x00 

19,200

6 0x06 0x00 38,400

3 0x03 0x00 

57,600

2 0x02 0x00 115,200

1 0x01 0x00

Type: I/O Register

(Size: 8 bits)

7

4

0

0

0

0

0

0

0

0

0

IER_DLM