Intel J1750 FH8065301562600 Manuale Utente
Codici prodotto
FH8065301562600
Power Management
66
Datasheet
by initiating a P_LVLx (P_LVL6) I/O read to all of the cores. States that require external
intervention and typically map back to processor core power states. States for
processor core include Normal (C0, C1).
intervention and typically map back to processor core power states. States for
processor core include Normal (C0, C1).
The processor core implements two software interfaces for requesting low power
states: MWAIT instruction extensions with sub-state specifies and P_LVLx reads to the
ACPI P_BLK register block mapped in the processor core’s I/O address space. The
P_LVLx I/O reads are converted to equivalent MWAIT C-state requests inside the
processor core and do not directly result in I/O reads on the processor core bus. The
monitor address does not need to be setup before using the P_LVLx I/O read interface.
The sub-state specifications used for each P_LVLx read can be configured in a software
programmable MSR by BIOS.
states: MWAIT instruction extensions with sub-state specifies and P_LVLx reads to the
ACPI P_BLK register block mapped in the processor core’s I/O address space. The
P_LVLx I/O reads are converted to equivalent MWAIT C-state requests inside the
processor core and do not directly result in I/O reads on the processor core bus. The
monitor address does not need to be setup before using the P_LVLx I/O read interface.
The sub-state specifications used for each P_LVLx read can be configured in a software
programmable MSR by BIOS.
The Cx state ends due to a break event. Based on the break event, the processor
returns the system to C0. The following are examples of such break events:
returns the system to C0. The following are examples of such break events:
•
Any unmasked interrupt goes active
•
Any internal event that will cause an NMI or SMI_B
•
CPU Pending Break Event (PBE_B)
•
MSI
6.3.4
Processor Core C-States Description
The following state descriptions assume that both threads are in common low power
state.
state.
6.3.4.1
Core C0 State
The normal operating state of a core where code is being executed.
Figure 8.
Idle Power Management Breakdown of the Processor Cores
Processor Package State
Core 1 State
Core 0 State