Goodram 2GB PC2-6400 GR800S264L6/2G Dépliant
Codici prodotto
GR800S264L6/2G
professional memory for everyone
BYTE
DESCRIPTION
0
Number of Serial PD Bytes written during module production
1
Total number of Bytes in Serial PD device
2
Fundamental Memory Type (FPM, EDO, SDRAM …)
3
Number of Row Addresses on this assembly
4
Number of Column Addresses on this assembly
5
Number of DIMM Banks
6
Data Width of this assembly
7
Data Width of this assembly
8
Voltage Interface Level of this assembly
9
SDRAM Cycle time at Maximum Supported CAS Latency (CL), CL=X
10
SDRAM Access from Clock
11
DIMM configuration type (Non-parity, Parity or ECC)
12
Refresh Rate/Type
13
Primary SDRAM Width
14
Error Checking SDRAM Width
15
SDRAM Device Attributes: Minimum Clock Delay, Back-to-Back RCA
16
SDRAM Device Attributes: Burst Lengths Supported
17
SDRAM Device Attributes: Number of Banks on SDRAM Device
18
SDRAM Device Attributes: CAS Latency
19
SDRAM Device Attributes: CS Latency
20
SDRAM Device Attributes: Write Latency/DIMM Type Information
21
SDRAM Module Attributes
22
SDRAM Device Attributes: General
23
Minimum Clock Cycle at CL = X - 0.5
24
Maximum Data Access Time (tAC) from Clock at CL = X - 0.5
25
Minimum Clock Cycle at CL = X - 1
26
Maximum Data Access Time (tAC) from Clock at CL = X - 1
27
Minimum Row Precharge Time (tRP)
28
Minimum Row Active to Row Active delay (tRRD)
29
Minimum RAS to CAS delay (tRCD)
30
Minimum Active to Precharge Time (tRAS)
31
Module Bank Density
32
Address and Command Input Setup Time Before Clock
33
Address and Command Input Hold Time After Clock
34
Data Input Setup Time Before Clock
35
Data Input Hold Time After Clock
36
Write recovery time (tWR)
37
Internal write to read command delay (tWTR)
38
Internal read to precharge command delay (tRTP)
39
Memory Analysis Probe Characteristics
40
Extension of Byte 41 tRC and Byte 42 tRFC
41
SDRAM Device Minimum Active to Active/Auto Refresh Time (tRC)
42
SDRAM Device Minimum Auto Refresh to Active/Auto Refresh (tRFC)
43
SDRAM Device Maximum device cycle time (tCKmax)
44
SDRAM Device Maximum skew between DQS and DQ signals (tDQSQ)
45
DDR SDRAM Device Maximum Read Data Hold Skew Factor (tQHS)
46
Reserved for future use
47
SDRAM Device Attributes - DDR SDRAM DIMM Height
48
Reserved for future use
49
Reserved for future use
50
Reserved for future use
51
Reserved for future use
52
Reserved for future use
53
Reserved for future use
54
Reserved for future use
55
Reserved for future use
56
Reserved for future use
57
Reserved for future use
58
Reserved for future use
59
Reserved for future use
60
Reserved for future use
61
Reserved for future use
62
SPD Revision
63
Checksum for Bytes 0-62
64-255
Manufacturer’s specific data
SPD CONFIGURATION
GOODRAM logo and GOODDRIVE logo are registered trademarks of Wilk Elektronik S.A.
All other trademarks and logos are the property of their respective owners.
All products and specifications are subject to change without notice.
Rev. 10.07.2008
All other trademarks and logos are the property of their respective owners.
All products and specifications are subject to change without notice.
Rev. 10.07.2008
Wilk Elektronik S.A.
Poland, 43-174 Łaziska Górne, ul. Mikołowska 42
tel.: 0-32/ 736 90 00, fax: 0-32/ 736 90 01
www.wilk.com.pl
Poland, 43-174 Łaziska Górne, ul. Mikołowska 42
tel.: 0-32/ 736 90 00, fax: 0-32/ 736 90 01
www.wilk.com.pl
l
www.goodram.com
© Wilk Elektronik S.A. 2008
www.goodram.com
MEMORY MODULE SPECIFICATION
HEX
DEC
0x80
128
0x08
8
0x08
8
0x0E
14
0x0A
10
0x61
97
0x40
64
0x00
0
0x05
5
0x25
37
0x40
64
0x00
0
0x82
130
0x08
8
0x00
0
0x00
0
0x0C
12
0x08
8
0x70
112
0x01
1
0x04
4
0x00
0
0x07
7
0x30
48
0x45
69
0x3D
61
0x50
80
0x3C
60
0x1E
30
0x3C
60
0x2D
45
0x01
1
0x17
23
0x25
37
0x05
5
0x12
18
0x3C
60
0x1E
30
0x1E
30
0x00
0
0x06
6
0x39
57
0x7F
127
0x80
128
0x14
20
0x1E
30
0x00
0
0x51
81
0x00
0
0x00
0
0x00
0
0x00
0
0x00
0
0x00
0
0x00
0
0x00
0
0x00
0
0x00
0
0x00
0
0x00
0
0x00
0
0x00
0
0x11
17
0x30
48