Acer Intel Celeron G460 KC.G0001.460 Manuale Utente

 Processor on 0.13 Micron Process in the 478-Pin Package Datasheet

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NOTE: VID_GOOD is not a processor signal. This signal is routed to the output enable pin of the voltage 

regulator control silicon. For more information on implementation refer to the Processor Platform Design 
Guide.

1. This timing diagram is not intended to show specific times. Instead a general ordering of events with respect 

to time should be observed.

2. When VCCVID is less than 1V, VID_GOOD must be low.
3. Vcc must be disabled before VID[4:0] becomes invalid.

VID_GOOD is not a processor signal. This signal is routed to the output enable pin of the voltage 
regulator control silicon. For more information on implementation refer to the Processor Platform 
Design Guide.

BCLK

Vcc

PWRGOOD

RESET#

VCCVID

VID_GOOD

VID[4:0]

Tc

Td

Ta= 1ms minimum (VCCVID > 1V to VID_GOOD high)
Tb= 50ms maximum (VID_GOOD to Vcc valid maximum time)
Tc= T37 (PWRGOOD inactive pulse width)
Td= T36 (PWRGOOD to RESET# de-assertion time)

Ta

Tb

Vcc

PWRGOOD

VCCVID

VID_GOOD

VID[4:0]