Intel E5-1620 v3 BX80644E51620V3 Manuale Utente
Codici prodotto
BX80644E51620V3
Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families
19
Datasheet Volume One
Overview
• Home snoop based coherency
• 3-bit Node ID
• 46-bit physical addressing support
• No Intel QuickPath Interconnect bifurcation support
• Differential signaling
• Forwarded clocking
• Up to 8.0 GT/s data rate (up to 16 GB/s direction peak bandwidth per port)
• 3-bit Node ID
• 46-bit physical addressing support
• No Intel QuickPath Interconnect bifurcation support
• Differential signaling
• Forwarded clocking
• Up to 8.0 GT/s data rate (up to 16 GB/s direction peak bandwidth per port)
— All ports run at same operational frequency
— Reference Clock is 100 MHz
— Slow boot speed initialization at 50 MT/s
— Reference Clock is 100 MHz
— Slow boot speed initialization at 50 MT/s
• Common reference clocking (same clock generator for both sender and receiver)
• Intel® Interconnect Built-In-Self-Test (Intel® IBIST) for high-speed testability
• Polarity and Lane reversal (Rx side only)
• Intel® Interconnect Built-In-Self-Test (Intel® IBIST) for high-speed testability
• Polarity and Lane reversal (Rx side only)
1.2.5
Platform Environment Control Interface (PECI)
The PECI is a one-wire interface that provides a communication channel between a
PECI client (the processor) and a PECI master (the PCH).
PECI client (the processor) and a PECI master (the PCH).
• Supports operation at up to 2 Mbps data transfers
• Link layer improvements to support additional services and higher efficiency over
• Link layer improvements to support additional services and higher efficiency over
PECI 2.0 generation
• Services include CPU thermal and estimated power information, control functions
for power limiting, P-state and T-state control, and access for Machine Check
Architecture registers and PCI configuration space (both within the processor
package and downstream devices)
Architecture registers and PCI configuration space (both within the processor
package and downstream devices)
• PECI address determined by SOCKET_ID configuration
• Single domain (Domain 0) is supported
• Single domain (Domain 0) is supported
1.3
Power Management Support
1.3.1
Processor Package and Core States
• ACPI C-states as implemented by the following processor C-states:
— Package: PC0, PC1/PC1E, PC2, PC3, PC6 (Package C7 is not supported)
— Core: CC0, CC1, CC1E, CC3, CC6, CC7
— Core: CC0, CC1, CC1E, CC3, CC6, CC7
• Enhanced Intel SpeedStep® Technology
1.3.2
System States Support
• S0, S1, S3, S4, S5
1.3.3
Memory Controller
• Multiple CKE power down modes
• Multiple self-refresh modes
• Multiple self-refresh modes