Acer E3-1220 v3 KC.12201.3E3 Manuale Utente

In all modes, the frequency of system memory is the lowest frequency of all memory

modules placed in the system, as determined through the SPD registers on the

memory modules. The system memory controller supports one or two DIMM

connectors per channel. The usage of DIMM modules with different latencies is

allowed, but in that case, the worst latency (among two channels) will be used. For

dual-channel modes, both channels must have a DIMM connector populated and for

single-channel mode only a single-channel may have one or both DIMM connectors

populated.

The following sections describe the Just-in-Time Scheduling, Command Overlap, and

Out-of-Order Scheduling Intel FMA technology enhancements.

The memory controller has an advanced command scheduler where all pending

requests are examined simultaneously to determine the most efficient request to be

issued next. The most efficient request is picked from all pending requests and issued

to system memory Just-in-Time to make optimal use of Command Overlapping. Thus,

instead of having all memory access requests go individually through an arbitration

mechanism forcing requests to be executed one at a time, they can be started without

interfering with the current request allowing for concurrent issuing of requests. This

allows for optimized bandwidth and reduced latency while maintaining appropriate

command spacing to meet system memory protocol.

Command Overlap allows the insertion of the DRAM commands between the Activate,

Pre-charge, and Read/Write commands normally used, as long as the inserted

commands do not affect the currently executing command. Multiple commands can be

issued in an overlapping manner, increasing the efficiency of system memory protocol.

While leveraging the Just-in-Time Scheduling and Command Overlap enhancements,

the IMC continuously monitors pending requests to system memory for the best use of

bandwidth and reduction of latency. If there are multiple requests to the same open

page, these requests would be launched in a back-to-back manner to make optimum

use of the open memory page. This ability to reorder requests on the fly allows the

IMC to further reduce latency and increase bandwidth efficiency.

The system memory controller incorporates a Data Scrambling feature to minimize the

impact of excessive di/dt on the platform system memory VRs due to successive 1s

and 0s on the data bus. Past experience has demonstrated that traffic on the data bus

is not random and can have energy concentrated at specific spectral harmonics

creating high di/dt which is generally limited by data patterns that excite resonance

between the package inductance and on die capacitances. As a result, the system

memory controller uses a data scrambling feature to create pseudo-random patterns

on the system memory data bus to reduce the impact of any excessive di/dt.

Intel

®

 Xeon

®

 Processor E3-1200 v3 Product Family

June 2013

Datasheet – Volume 1 of 2

Order No.: 328907-001

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