Acer E3-1220 v3 KC.12201.3E3 Manuale Utente

Codici prodotto

KC.12201.3E3

Figure 13.

Thread and Core C-State Entry and Exit

C1E

MWAIT(C1), HLT

MWAIT(C7),

P_LVL4 I/O Read

MWAIT(C6),

P_LVL3 I/O Read

MWAIT(C3),

P_LVL2 I/O Read

MWAIT(C1), HLT

(C1E Enabled)

While individual threads can request low power C-states, power saving actions only

take place once the core C-state is resolved. Core C-states are automatically resolved

by the processor. For thread and core C-states, a transition to and from C0 is required

before entering any other C-state.

Table 16.

Coordination of Thread Power States at the Core Level

Processor Core C-State

Thread 1

Thread 0

Note: 1. If enabled, the core C-state will be C1E if all cores have resolved a core C1 state or higher.

4.2.3

Requesting Low-Power Idle States

The primary software interfaces for requesting low-power idle states are through the

MWAIT instruction with sub-state hints and the HLT instruction (for C1 and C1E).

However, software may make C-state requests using the legacy method of I/O reads

from the ACPI-defined processor clock control registers, referred to as P_LVLx. This

method of requesting C-states provides legacy support for operating systems that

initiate C-state transitions using I/O reads.

For legacy operating systems, P_LVLx I/O reads are converted within the processor to

the equivalent MWAIT C-state request. Therefore, P_LVLx reads do not directly result

in I/O reads to the system. The feature, known as I/O MWAIT redirection, must be

enabled in the BIOS.

The BIOS can write to the C-state range field of the PMG_IO_CAPTURE MSR to restrict

the range of I/O addresses that are trapped and emulate MWAIT like functionality.

Any P_LVLx reads outside of this range do not cause an I/O redirection to MWAIT(Cx)

like request. They fall through like a normal I/O instruction.

Processor—Power Management

Intel

Xeon

Processor E3-1200 v3 Product Family

Datasheet – Volume 1 of 2

June 2013

Order No.: 328907-001