Intel SR1640TH SR1640THNA Manuale Utente
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SR1640THNA
Functional Architecture
Intel® Server System SR1640TH TPS
Revision
1.0
Intel order number: E94847-001
10
memory. Each DDR3 channel in the IMC supports up to two DDR3 RDIMM/UDIMM slots.
The DDR3 RDIMM frequency can be 800/1066/1333 MHz. DDR3 UDIMM frequency can be
1066/1333 MHz. All RDIMMs and UDIMMs include ECC (Error Correction Code) operation.
Various speeds and memory technologies are supported.
The DDR3 RDIMM frequency can be 800/1066/1333 MHz. DDR3 UDIMM frequency can be
1066/1333 MHz. All RDIMMs and UDIMMs include ECC (Error Correction Code) operation.
Various speeds and memory technologies are supported.
The Intel
®
Core
™
i3 series processor has an Integrated Memory Controller (IMC) supports
DDR3 protocols with two independent, 64-bit wide channels each accessing one or two
DIMMs. Only DDR3 UDIMM can be supported with the Intel
DIMMs. Only DDR3 UDIMM can be supported with the Intel
®
Core
™
i3 series processor.
RAS (Reliability, Availability, and Serviceability) is not supported on the server board
S3420TH in Intel
S3420TH in Intel
®
Server System SR1640TH.
2.4.3.1
Memory Sizing and Configuration
The server board S3420TH in Intel
®
Server System SR1640TH supports various memory
module sizes and configurations. These combinations of sizes and configurations are valid
only for DDR3 DIMMs approved by Intel
only for DDR3 DIMMs approved by Intel
®
Corporation.
Server board BIOS supports:
z
DIMM sizes of 1 GB, 2 GB, and 4 GB.
z
DIMMs composed of DRAM using 2 Gb technology.
z
DRAMs organized as single rank, dual rank, or quad rank DIMMS.
z
DIMM speeds of 800, 1066, or 1333 MT/s.
z
Registered or Unregistered (unbuffered) DIMMs (RDIMMs or UDIMMs).
Note: UDIMMs should be ECC, and may or may not have thermal sensors; RDIMMs must
have ECC and must have thermal sensors.
have ECC and must have thermal sensors.
Server board S3420TH BIOS has the below limitations:
256 Mb technology, x4 DRAM on UDIMM, and quad rank UDIMM are NOT
supported
supported
x16 DRAM on UDIMM is not supported on combo routing
Memory suppliers not productizing native 800 ECC UDIMMs
Intel
®
Xeon
®
3400 Series support all timings defined by JEDEC.
256 Mb/512 Mb technology, x4 and x16 DRAMs on RDIMM are NOT supported
All channels in a system will run at the fastest common frequency
No mixing of registered and unbuffered DIMMs
No mixing of different ranks or speeds on UDIMM or RDIMM.
2.4.3.2
Post Error Codes
The range {0xE0 - 0xEF} of POST codes is used for memory errors in early POST. In late
POST, this range is used for reporting other system errors.
POST, this range is used for reporting other system errors.
z
0xE8 - No Usable Memory Error: If no memory is available, the system emits
POST Diagnostic LED code 0xE8 and halts the system.
POST Diagnostic LED code 0xE8 and halts the system.
z
0xE8 - Configuration Error: If a DDR3 DIMM has no SPD information, the BIOS
treats the DIMM slot as if no DDR3 DIMM is present on it. Therefore, if this is the
only DDR3 DIMM installed in the system, the BIOS halts with POST Diagnostic LED
code 0xE8 (no usable memory) and halts the system.
treats the DIMM slot as if no DDR3 DIMM is present on it. Therefore, if this is the
only DDR3 DIMM installed in the system, the BIOS halts with POST Diagnostic LED
code 0xE8 (no usable memory) and halts the system.