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Electrical Specifications

Dual-Core Intel

Xeon

Processor 5100 Series Datasheet

2.4.2

PLL Power Supply

An on-die PLL filter solution is implemented on the Dual-Core Intel

Xeon

Processor

5100 Series. The

CCPLL

input is used for this configuration in Dual-Core Intel

Xeon

Processor 5100 Series based platforms. Please refer to

Table 2-13

for DC specifications.

Refer to the appropriate platform design guidelines for decoupling and routing
guidelines.

2.5

Voltage Identification (VID)

The Voltage Identification (VID) specification for the Dual-Core Intel

Xeon

Processor

5100 Series is defined by the Voltage Regulator Module (VRM) and Enterprise Voltage
Regulator-Down (EVRD) 11.0 Design Guidelines. The voltage set by the VID signals is
the reference VR output voltage to be delivered to the processor Vcc pins. VID signals
are open drain outputs, which must be pulled up to V

. Please refer to

Table 2-16

for

the DC specifications for these signals. A voltage range is provided in

Table 2-13

and

changes with frequency. The specifications have been set such that one voltage
regulator can operate with all supported frequencies.

Individual processor VID values may be calibrated during manufacturing such that two
devices at the same core frequency may have different default VID settings. This is
reflected by the VID range values provided in

Table 2-3

The Dual-Core Intel

Xeon

Processor 5100 Series uses six voltage identification

signals, VID[6:1], to support automatic selection of power supply voltages.

Table 2-3

specifies the voltage level corresponding to the state of VID[6:1]. A ‘1’ in this table
refers to a high voltage level and a ‘0’ refers to a low voltage level. The definition
provided in

Table 2-3

is not related in any way to previous Intel

Xeon

processors or

voltage regulator designs. If the processor socket is empty (VID[6:1] = 111111), or
the voltage regulation circuit cannot supply the voltage that is requested, the voltage
regulator must disable itself. See the Voltage Regulator Module (VRM) and Enterprise
Voltage Regulator-Down (EVRD) 11.0 Design Guidelines for further details.

Although the Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down
(EVRD) 11.0 Design Guidelines defines VID[7:0], VID[7] and VID[0] are not used on
the Dual-Core Intel

Xeon

Processor 5100 Series.

The Dual-Core Intel

Xeon

Processor 5100 Series provides the ability to operate while

transitioning to an adjacent VID and its associated processor core voltage (V

). This

will represent a DC shift in the load line. It should be noted that a low-to-high or high-
to-low voltage state change may result in as many VID transitions as necessary to
reach the target core voltage. Transitions above the specified VID are not permitted.

Table 2-13

includes VID step sizes and DC shift ranges. Minimum and maximum

voltages must be maintained as shown in

Table 2-14

and

Table 2-2

The VRM or EVRD utilized must be capable of regulating its output to the value defined
by the new VID. DC specifications for dynamic VID transitions are included in

Table 2-13

and

Table 2-14

Reserved

Table 2-2.

BSEL[2:0] Frequency Table (Sheet 2 of 2)

BSEL2

BSEL1

BSEL0

Bus Clock Frequency