Fujifilm Xeon 5050 S26361-F3248-L300 Scheda Tecnica

Dual-Core Intel® Xeon® Processor 5000 Series Datasheet

21

1.

The MS_ID[1:0] signals are provided to indicate the Market Segment for the processor and may be used 

for future processor compatibility or for keying. System management software may utilize these signals to 

identify the processor installed.

2.

These signals are not connected to the processor die.

3.

A logic 0 is achieved by pulling the signal to ground on the package.

4.

A logic 1 is achieved by leaving the signal as a no connect on the package.

All Reserved signals must remain unconnected. Connection of these signals to V

CC

, V

TT

, 

V

SS

, or to any other signal (including each other) can result in component malfunction 

or incompatibility with future processors. See 

 for a land 

listing of the processor and the location of all Reserved signals.

For reliable operation, always connect unused inputs or bidirectional signals to an 
appropriate signal level. Unused active high inputs, should be connected through a 
resistor to ground (V

SS

). Unused outputs can be left unconnected; however, this may 

interfere with some TAP functions, complicate debug probing, and prevent boundary 
scan testing. A resistor must be used when tying bidirectional signals to power or 
ground. When tying any signal to power or ground, a resistor will also allow for system 
testability. Resistor values should be within ± 20% of the impedance of the baseboard 
trace for FSB signals. For unused AGTL+ input or I/O signals, use pull-up resistors of 
the same value as the on-die termination resistors (R

TT

). 

TAP, Asynchronous GTL+ inputs, and Asynchronous GTL+ outputs do not include on-die 
termination. Inputs and utilized outputs must be terminated on the baseboard. Unused 
outputs may be terminated on the baseboard or left unconnected. Note that leaving 
unused outputs unterminated may interfere with some TAP functions, complicate debug 
probing, and prevent boundary scan testing. Signal termination for these signal types 
is discussed in the appropriate platform design guidelines.

The TESTHI signals must be tied to the processor V

TT

 using a matched resistor, where a 

matched resistor has a resistance value within +/-20% of the impedance of the board 
transmission line traces. For example, if the trace impedance is 50 Ω, then a value 

between 40 Ω and 60 Ω is required. 

The TESTHI signals may use individual pull-up resistors or be grouped together as 
detailed below. A matched resistor must be used for each group:

• TESTHI[1:0] - can be grouped together with a single pull-up to V

TT

• TESTHI[7:2] - can be grouped together with a single pull-up to V

TT

• TESTHI8 – cannot be grouped with other TESTHI signals
• TESTHI9 – cannot be grouped with other TESTHI signals
• TESTHI10 – cannot be grouped with other TESTHI signals
• TESTHI11 – cannot be grouped with other TESTHI signals

The FSB signals have been combined into groups by buffer type. AGTL+ input signals 
have differential input buffers, which use GTLREF as a reference level. In this 
document, the term “AGTL+ Input” refers to the AGTL+ input group as well as the 
AGTL+ I/O group when receiving. Similarly, “AGTL+ Output” refers to the AGTL+ 
output group as well as the AGTL+ I/O group when driving. AGTL+ asynchronous 
outputs can become active anytime and include an active PMOS pull-up transistor to 
assist the during the first clock of a low-to-high voltage transition.