Intel 2 Extreme X7900 LF80537GG0724ML Manuale Utente

16

Datasheet

In the Sleep state, the processor is incapable of responding to snoop transactions or 

latching interrupt signals. No transitions or assertions of signals (with the exception of 

SLP#, DPSLP# or RESET#) are allowed on the FSB while the processor is in Sleep 

state. Snoop events that occur while in Sleep state or during a transition into or out of 

Sleep state causes unpredictable behavior. Any transition on an input signal before the 

processor has returned to the Stop-Grant state results in unpredictable behavior.

If RESET# is driven active while the processor is in the Sleep state, and held active, 

then the processor resets itself, ignoring the transition through Stop-Grant state. If 

RESET# is driven active while the processor is in the Sleep state, the SLP# and 

STPCLK# signals should be deasserted immediately after RESET# is asserted to ensure 

the processor correctly executes the Reset sequence.

While in the Sleep state, the processor is capable of entering an even lower power 

state, the Deep Sleep state, by asserting the DPSLP# pin (See 

). While 

the processor is in the Sleep state, the SLP# pin must be deasserted if another 

asynchronous FSB event needs to occur. 

The Deep Sleep state is entered through assertion of the DPSLP# pin while in the Sleep 

state. BCLK may be stopped during the Deep Sleep state for additional platform-level 

power savings. BCLK stop/restart timings on appropriate chipset based platforms with 

the CK505 clock chip are as follows:

• Deep Sleep entry: the system clock chip may stop/tristate BCLK within 2 BCLKs of 

DPSLP# assertion. It is permissible to leave BCLK running during Deep Sleep.

• Deep Sleep exit: the system clock chip must drive BCLK to differential DC levels 

within 2-3 ns of DPSLP# deassertion and start toggling BCLK within 10 BCLK 

periods.

To re-enter the Sleep state, the DPSLP# pin must be deasserted. BCLK can be re-

started after DPSLP# deassertion as described above. A period of 15 microseconds (to 

allow for PLL stabilization) must occur before the processor can be considered to be in 

the Sleep state. Once in the Sleep state, the SLP# pin must be deasserted to re-enter 

the Stop-Grant state.

While in Deep Sleep state, the processor is incapable of responding to snoop 

transactions or latching interrupt signals. No transitions of signals are allowed on the 

FSB while the processor is in Deep Sleep state. When the processor is in Deep Sleep 

state, it does not respond to interrupts or snoop transactions. Any transition on an 

input signal before the processor has returned to Stop-Grant state results in 

unpredictable behavior.

The Deeper Sleep state is similar to the Deep Sleep state but further reduces core 

voltage levels. One of the potential lower core voltage levels is achieved by entering the 

base Deeper Sleep state. The Deeper Sleep state is entered through assertion of the 

DPRSTP# pin while in the Deep Sleep state. The other lower core voltage level, the 

lowest possible in the processor, is achieved by entering the Intel Enhanced Deeper 

Sleep state which is a sub-state of Deeper Sleep state. Intel Enhanced Deeper Sleep 

state is entered through assertion of the DPRSTP# pin while in the Deep Sleep only 

when the L2 cache has been completely shut down. Refer to 

 and 

 for further details on reducing the L2 cache and entering Intel 

Enhanced Deeper Sleep state.

In response to entering Deeper Sleep, the processor drives the VID code corresponding 

to the Deeper Sleep core voltage on the VID[6:0] pins.