Texas Instruments IC FLPT TMS320C28346ZFET PBGA-256 TID TMS320C28346ZFET Scheda Tecnica
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TMS320C28346ZFET
SPRS516D – MARCH 2009 – REVISED AUGUST 2012
6.7.3
Device Clock Table
This section provides the timing requirements and switching characteristics for the various clock options
available.
available.
through
list the cycle times of various clocks.
Table 6-4. Clocking and Nomenclature (300-MHz Devices)
MIN
NOM
MAX
UNIT
t
c(OSC)
, Cycle time
33.3
125
ns
On-chip oscillator clock (crystal/resonator–X1/X2)
Frequency
8
30
MHz
t
c(CI)
, Cycle time (C8)
6.67
50
ns
PLL enabled
Frequency
2
150
MHz
XCLKIN
(1)
t
c(CI)
, Cycle time (C8)
6.67
250
ns
PLL disabled
Frequency
4
150
MHz
t
c(CI)
, Cycle time (C8)
10
50
ns
PLL enabled
Frequency
2
100
MHz
X1
(1)
t
c(CI)
, Cycle time (C8)
10
250
ns
PLL disabled
Frequency
4
100
MHz
t
c(SCO)
, Cycle time
3.33
500
ns
SYSCLKOUT
Frequency
2
300
MHz
t
c(XCO)
, Cycle time
13.3
2000
ns
XCLKOUT
Frequency
0.5
75
(2)
MHz
t
c(HCO)
, Cycle time
25
ns
HSPCLK/EXTADCCLK
(3)
Frequency
40
MHz
t
c(LCO)
, Cycle time
6.67
13.3
(5)
ns
LSPCLK
(4)
Frequency
75
(5)
150
MHz
(1)
The input clock frequency and PLLCR[DIV] values should be chosen such that the output frequency of the PLL(VCOCLK) lies between
400 MHz to 600 MHz.
400 MHz to 600 MHz.
(2)
Although the maximum XCLKOUT frequency is 75 MHz, this value may not be attainable depending on SYSCLKOUT and available
prescalers.
prescalers.
(3)
This frequency is limited by GPIO switching characteristics.
(4)
Lower LSPCLK and HSPCLK will reduce device power consumption.
(5)
This is the value if SYSCLKOUT = 300 MHz.
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Electrical Specifications
115
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