Texas Instruments LM3402HV Evaluation Board LM3402HVEVAL/NOPB LM3402HVEVAL/NOPB Scheda Tecnica
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LM3402HVEVAL/NOPB
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SNVS450E – SEPTEMBER 2006 – REVISED MAY 2013
Layout Considerations
The performance of any switching converter depends as much upon the layout of the PCB as the component
selection. The following guidelines will help the user design a circuit with maximum rejection of outside EMI and
minimum generation of unwanted EMI.
selection. The following guidelines will help the user design a circuit with maximum rejection of outside EMI and
minimum generation of unwanted EMI.
COMPACT LAYOUT
Parasitic inductance can be reduced by keeping the power path components close together and keeping the
area of the loops that high currents travel small. Short, thick traces or copper pours (shapes) are best. In
particular, the switch node (where L1, D1, and the SW pin connect) should be just large enough to connect all
three components without excessive heating from the current it carries. The LM3402/02HV operates in two
distinct cycles whose high current paths are shown in
area of the loops that high currents travel small. Short, thick traces or copper pours (shapes) are best. In
particular, the switch node (where L1, D1, and the SW pin connect) should be just large enough to connect all
three components without excessive heating from the current it carries. The LM3402/02HV operates in two
distinct cycles whose high current paths are shown in
:
Figure 31. Buck Converter Current Loops
The dark grey, inner loop represents the high current path during the MOSFET on-time. The light grey, outer loop
represents the high current path during the off-time.
represents the high current path during the off-time.
GROUND PLANE AND SHAPE ROUTING
The diagram of
is also useful for analyzing the flow of continuous current vs. the flow of pulsating
currents. The circuit paths with current flow during both the on-time and off-time are considered to be continuous
current, while those that carry current during the on-time or off-time only are pulsating currents. Preference in
routing should be given to the pulsating current paths, as these are the portions of the circuit most likely to emit
EMI. The ground plane of a PCB is a conductor and return path, and it is susceptible to noise injection just as
any other circuit path. The continuous current paths on the ground net can be routed on the system ground plane
with less risk of injecting noise into other circuits. The path between the input source and the input capacitor and
the path between the recirculating diode and the LEDs/current sense resistor are examples of continuous current
paths. In contrast, the path between the recirculating diode and the input capacitor carries a large pulsating
current. This path should be routed with a short, thick shape, preferably on the component side of the PCB.
Multiple vias in parallel should be used right at the pad of the input capacitor to connect the component side
shapes to the ground plane. A second pulsating current loop that is often ignored is the gate drive loop formed
by the SW and BOOT pins and capacitor CB. To minimize this loop at the EMI it generates, keep CB close to the
SW and BOOT pins.
current, while those that carry current during the on-time or off-time only are pulsating currents. Preference in
routing should be given to the pulsating current paths, as these are the portions of the circuit most likely to emit
EMI. The ground plane of a PCB is a conductor and return path, and it is susceptible to noise injection just as
any other circuit path. The continuous current paths on the ground net can be routed on the system ground plane
with less risk of injecting noise into other circuits. The path between the input source and the input capacitor and
the path between the recirculating diode and the LEDs/current sense resistor are examples of continuous current
paths. In contrast, the path between the recirculating diode and the input capacitor carries a large pulsating
current. This path should be routed with a short, thick shape, preferably on the component side of the PCB.
Multiple vias in parallel should be used right at the pad of the input capacitor to connect the component side
shapes to the ground plane. A second pulsating current loop that is often ignored is the gate drive loop formed
by the SW and BOOT pins and capacitor CB. To minimize this loop at the EMI it generates, keep CB close to the
SW and BOOT pins.
CURRENT SENSING
The CS pin is a high-impedance input, and the loop created by R
SNS
, R
Z
(if used), the CS pin and ground should
be made as small as possible to maximize noise rejection. R
SNS
should therefore be placed as close as possible
to the CS and GND pins of the IC.
REMOTE LED ARRAYS
In some applications the LED or LED array can be far away (several inches or more) from the LM3402/02HV, or
on a separate PCB connected by a wiring harness. When an output capacitor is used and the LED array is large
or separated from the rest of the converter, the output capacitor should be placed close to the LEDs to reduce
the effects of parasitic inductance on the AC impedance of the capacitor. The current sense resistor should
remain on the same PCB, close to the LM3402/02HV.
on a separate PCB connected by a wiring harness. When an output capacitor is used and the LED array is large
or separated from the rest of the converter, the output capacitor should be placed close to the LEDs to reduce
the effects of parasitic inductance on the AC impedance of the capacitor. The current sense resistor should
remain on the same PCB, close to the LM3402/02HV.
Copyright © 2006–2013, Texas Instruments Incorporated
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