Texas Instruments CDCLVP2108EVM - CDCLVP2108 Evaluation Module CDCLVP2108EVM CDCLVP2108EVM Scheda Tecnica
Codici prodotto
CDCLVP2108EVM
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Output Clock
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Schematics and Layout
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Output Clock
The CDCLVP2108 generates up to 16 LVPECL outputs. Four outputs are available on the
CDCLVP2108EVM (outputs 0, 7, 8, and 15) through the following SMAs:
CDCLVP2108EVM (outputs 0, 7, 8, and 15) through the following SMAs:
•
J13, J23 for OUT0
•
J17, J27 for OUT7
•
J33, J32 for OUT8
•
J39, J38 for OUT15
The LVPECL outputs are terminated with 150
Ω
to ground and ac-coupled to the respective SMAs.
through
show the printed circuit board (PCB) schematics.
Note:
Board layouts are not to scale. These figures are intended to show how the board is laid out;
they are not intended to be used for manufacturing CDCLVP2108EVM PCBs.
they are not intended to be used for manufacturing CDCLVP2108EVM PCBs.
SCAU030 – May 2009
Low Additive Phase Noise Clock Buffer Evaluation Board
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