Texas Instruments CDCLVP1212EVM - CDCLVP1212 Evaluation Module CDCLVP1212EVM CDCLVP1212EVM Scheda Tecnica
Codici prodotto
CDCLVP1212EVM
User's Guide
SCAU036 – August 2009
Low Additive Phase Noise Clock Buffer Evaluation Board
Figure 1. CDCLVP1212EVM Evaluation Board
Features:
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Easy-to-use evaluation board to fan out low phase noise clocks
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Easy device setup
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Fast configuration
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Control pins configurable through jumpers
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Board powered at +2.5-V/+3.3-V
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Single-ended or differential input clocks
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CDCLVP1212 supports 12 LVPECL outputs; CDCLVP1212EVM supports four LVPECL outputs
Contents
1
General Description
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2
Signal Path and Control Circuitry
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3
Getting Started
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4
Input Clock Selection
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5
Output Clock
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6
Schematics and Layout
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List of Figures
1
CDCLVP1212EVM Evaluation Board
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2
CDCLVP1212EVM—Schematic
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3
CDCLVP1212EVM—Schematic
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4
CDCLVP1212EVM—Schematic
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1
SCAU036 – August 2009
Low Additive Phase Noise Clock Buffer Evaluation Board
Copyright © 2009, Texas Instruments Incorporated