Texas Instruments CDCLVC1310-EVM - CDCLVC1310 Evaluation Module CDCLVC1310-EVM CDCLVC1310-EVM Scheda Tecnica
Codici prodotto
CDCLVC1310-EVM
User
'
s Guide
SCAU046
–
December 2011
10-Output Low Jitter Low Power Differential to LVCMOS
Clock Buffer - Evaluation Board
The CDCLVC1310 is a highly versatile, low jitter and low power clock fan out buffer, which distributes up
to ten low jitter LVCMOS clock outputs. The clock is derived from one of three inputs, whose primary and
secondary inputs feature differential or single-ended signals and the third input is a crystal input.
to ten low jitter LVCMOS clock outputs. The clock is derived from one of three inputs, whose primary and
secondary inputs feature differential or single-ended signals and the third input is a crystal input.
This evaluation module (EVM) is designed to demonstrate the electrical performance of the
CDCLVC1310. Throughout this document, the acronym EVM and the phrases evaluation module and
evaluation board are synonymous with the CDCLVC1310EVM.
CDCLVC1310. Throughout this document, the acronym EVM and the phrases evaluation module and
evaluation board are synonymous with the CDCLVC1310EVM.
and
illustrate the
CDCLVC1310EVM.
For optimum performance, the board is equipped with 50-
Ω
SMA connectors and well-controlled 50-
Ω
impedance microstrip transmission lines.
Contents
1
Features
......................................................................................................................
2
Signal Path and Control Circuit
...........................................................................................
3
Getting Started
..............................................................................................................
4
Power Supply Connections
................................................................................................
5
Input Clock Selection
.......................................................................................................
6
Output Clock
.................................................................................................................
7
Bill of Materials
..............................................................................................................
8
Schematics
...................................................................................................................
List of Figures
1
Schematic
–
CDCLVC1310 and Control Pins (Page 1 of 5)
..........................................................
2
Schematic
–
Inputs (Page 2 of 5)
.........................................................................................
3
Schematic
–
Power Supply Filter Networks (Page 3 of 5)
.............................................................
4
Schematic
–
Outputs Y0 to Y4 (Page 4 of 5)
...........................................................................
5
Schematic
–
Outputs Y5 to Y9 (Page 5 of 5)
...........................................................................
List of Tables
1
Input Selection
...............................................................................................................
2
Bill of Materials
..............................................................................................................
1
Features
•
Easy-to-use evaluation board to fan out low phase-noise clocks
•
Easy device setup
•
Fast configuration
•
Control pins configurable through jumpers
•
Board powered at 2.5-/3.3-V for VDD and at 1.5-/1.8-/2.5-/3.3-V for VDDO
•
Single-ended or differential input clocks or crystal input
1
SCAU046
–
December 2011
10-Output Low Jitter Low Power Differential to LVCMOS Clock Buffer -
Evaluation Board
Copyright
©
2011, Texas Instruments Incorporated