Microchip Technology IC MCU 8BIT PIC18F65K22-I/PT TQFP-64 MCP PIC18F65K22-I/PT Scheda Tecnica
Codici prodotto
PIC18F65K22-I/PT
2009-2011 Microchip Technology Inc.
DS39960D-page 307
PIC18F87K22 FAMILY
21.4.4.5
Clock Synchronization and
the CKP bit
the CKP bit
When the CKP bit is cleared, the SCLx output is forced
to ‘0’. However, clearing the CKP bit will not assert the
SCLx output low until the SCLx output is already
sampled low. Therefore, the CKP bit will not assert the
SCLx line until an external I
to ‘0’. However, clearing the CKP bit will not assert the
SCLx output low until the SCLx output is already
sampled low. Therefore, the CKP bit will not assert the
SCLx line until an external I
2
C master device has
already asserted the SCLx line. The SCLx output will
remain low until the CKP bit is set and all other
devices on the I
remain low until the CKP bit is set and all other
devices on the I
2
C bus have deasserted SCLx. This
ensures that a write to the CKP bit will not violate the
minimum high time requirement for SCLx (see
minimum high time requirement for SCLx (see
).
FIGURE 21-14:
CLOCK SYNCHRONIZATION TIMING
SDAx
SCLx
DX – 1
DX
WR
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
SSPxCON1
CKP
Master Device
Deasserts Clock
Deasserts Clock
Master Device
Asserts Clock
Asserts Clock