Texas Instruments 2-A Peak Sink/Source DDR Termination Regulator With VTTREF Buffered Reference TPS51206EVM-745 TPS51206EVM-745 Scheda Tecnica

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The TPS51206EVM-745 evaluation module (EVM) uses the TPS51206. The TPS51206 is a sink/source
double data rate (DDR) termination regulator with VTTREF buffered reference output. It is specifically
designed for low-input voltage, low cost, low external component count systems where space is a key
consideration.

1

Description

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1.1

Typical Applications

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1.2

Features

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2

Electrical Performance Specifications

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3

Schematics

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4

Test Setup

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4.1

Test Equipment

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4.2

Recommended Wire Gauge

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4.3

Recommended Test Setup

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5

Configurations

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5.1

Transient Load Selection

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5.2

Source Transient Load Selection

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5.3

Sink Transient Load Selection

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5.4

S1, S2 Enable Selection

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6

Test Procedure

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6.1

DDR2 (0.9VTT)/DDR3 (0.75VTT)/DDR3L (0.675VTT)/DDR4 (0.6VTT) Source Load Regulation

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6.2

DDR2 (0.9VTT)/DDR3 (0.75VTT)/DDR3L (0.675VTT)/DDR4 (0.6VTT) Sink/Source Current
Transient

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6.3

DDR2 (0.9VTT)/DDR3 (0.75VTT)/DDR3L (0.675VTT)/DDR4 (0.6VTT) Loop Stability
Measurement

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6.4

List of Test Points

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6.5

Equipment Shutdown

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7

Performance Data and Typical Characteristic Curves

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7.1

VTT Load Regulation

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7.2

VTTREF Load Regulation

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7.3

VTT Dropout Voltage

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7.4

VTT Sink/Source Load Transient

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7.5

DDR3(0.75VTT) S5 Enable Turnon/Turnoff

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7.6

DDR3 (0.75VTT) S3 Enable Turnon/Turnoff

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7.7

DDR3 (0.75VTT) Bode Plot

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8

EVM Assembly Drawing and PCB Layout

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9

Bill of Materials

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1

TPS51206EVM-745, Schematic 1

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2

TPS51206EVM-745, Schematic 2

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1

SLUU515

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August 2011

Copyright

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2011, Texas Instruments Incorporated