Texas Instruments SN65HVD101 and SN65HVD102 Evaluation Module for IO-LINK PHY for Device Nodes SN65HVD101EVM SN65HVD101EVM Scheda Tecnica
Codici prodotto
SN65HVD101EVM
EVM Setup and Precautions
Figure 2. SN65HVD101 EVM Board Layout
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EVM Setup and Precautions
To evaluate the performance of the SN65HVD101 you need the following equipment:
1. Power supply capable of supplying 3.3 V. 5 V if using the SN65HVD102 device.
2. Power supply capable of supplying 24 V across Lp (supply) and Ln (GND), if using the SN65HVD101
device.
device.
3. Oscilloscope note: The IO-Link uses industrial 24-V signaling; oscilloscope probes should be chosen
which will not be damaged by voltage levels up to 30 V.
which will not be damaged by voltage levels up to 30 V.
4. IO-Link Master Node with appropriate 3-wire cable with Lp, Ln and CQ signals.
5. Local microcontroller, or equivalent, to communicate with the SN65HVD10x IO-Link PHY via the
controller interface pins.
controller interface pins.
3.1
SN65HVD101 EVM Setup
With an appropriate IO-Link cable, connect the Lp, Ln, and CQ pins from TB1 on the EVM board to an IO-
Link Master node.
Link Master node.
3.3-V or 5-V supply operation
On JMP2 if a shunt is placed on VCC_SET to GND, the internal voltage regulator will supply 3.3 V. If no
shunt is placed on JMP2, the VCC_SET input will float and the internal regulator will supply 5 V.
shunt is placed on JMP2, the VCC_SET input will float and the internal regulator will supply 5 V.
On the SN65HVD101 device, VCC_IN is a voltage-sense feedback signal. When using the SN65HVD101
EVM, place a shunt over VCC_IN and VCC_OUT on JMP8.
EVM, place a shunt over VCC_IN and VCC_OUT on JMP8.
ILIM_ADJ – Current Limit Adjust
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SLLU178 – February 2013
SN65HVD101 and SN65HVD102 EVM User's Guide
Copyright © 2013, Texas Instruments Incorporated