Texas Instruments Evaluation Kit for DS99R105 DS99R106 FPD-Link II Serializer and Deserializer Chipset SERDES05-40USB/NO SERDES05-40USB/NOPB Scheda Tecnica
Codici prodotto
SERDES05-40USB/NOPB
Application Report
SNLA102B – May 2008 – Revised April 2013
AN-1807 FPD-Link II Display SerDes Overview
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ABSTRACT
TI’s FPD-Link II family of embedded clock LVDS SerDes provide enhanced features, and improved signal
quality over prior generations of FPD-Link SerDes devices for Display applications. FPD-Link Chipsets
serialized the wide parallel RGB buses down to 4 or 5 pairs of LVDS signaling depending upon the
chipset. 18-bit RGB was serialized to three LVDS data lines and a LVDS clock, while 24-bit RGB was
serialized to four LVDS data lines and a LVDS clock. This provided a smaller, higher speed video bus and
has become the defacto standard for Notebook Display interfaces.
quality over prior generations of FPD-Link SerDes devices for Display applications. FPD-Link Chipsets
serialized the wide parallel RGB buses down to 4 or 5 pairs of LVDS signaling depending upon the
chipset. 18-bit RGB was serialized to three LVDS data lines and a LVDS clock, while 24-bit RGB was
serialized to four LVDS data lines and a LVDS clock. This provided a smaller, higher speed video bus and
has become the defacto standard for Notebook Display interfaces.
Contents
1
Introduction
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2
The SERIALIZER Function
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3
The DESERIALIZER Function
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4
Serial Payload
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5
Streaming RGB Display Applications
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6
Signal Quality Enhancers
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7
EMI Mitigation Features
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8
Current FPD-Link II SerDes Devices
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9
Summary
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List of Figures
1
General Block Diagram – FPD-Link II 18-bit RGB Display Application
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2
24-bit Serial Payload Example
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3
24-bit RGB FPD-Link II SERDES XGA Display Application
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List of Tables
1
Select FPD-Link II SER and DES Device Comparison Table
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1
SNLA102B – May 2008 – Revised April 2013
AN-1807 FPD-Link II Display SerDes Overview
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