Texas Instruments XILINXPWR-081 Evaluation Module for Xilinx FPGAs XILINXPWR-081 XILINXPWR-081 Scheda Tecnica
Codici prodotto
XILINXPWR-081
SLVL004
XILINXPWR-081 (HPA-081)
Single-Channel Linear Regulator Power Management Solution Providing I
CCINT
up to 1.4
A from V
IN
= 3.3 V and 800 mA from V
IN
= 5.0 V
SUPPORTS :
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-
Spartan™-3 Design 3 (PR215) -
http://focus.ti.com/lit/ml/slva176/slva176.pdf
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Spartan™-II Design 2 (PR209) -
http://focus.ti.com/lit/ml/slva170/slva170.pdf
o
Board requires significant modification to match PR209
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Spartan™-IIE Design 2 (PR210) -
http://focus.ti.com/lit/ml/slva171/slva171.pdf
o
Board requires significant modification to match PR210
FEATURES:
-
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Independent linear regulators allow higher power dissipation than an integrated
dual-channel solution.
dual-channel solution.
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-
Linear regulator solution saves cost and space over a switching DC/DC solution.
-
-
Control cost by using lower current LDOs from the TPS79xxx family for U2, U3
and U4 to meet specific application requirements.
and U4 to meet specific application requirements.
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-
Linear regulators start- up fast, allowing large in-rush currents for charging
decoupling capacitors and FPGA start-up. The current draw on the input power
supply is minimized by the use of the:
decoupling capacitors and FPGA start-up. The current draw on the input power
supply is minimized by the use of the:
o
External SVS, U1, which monitors the input rail and prevents the regulator
from enabling until the input bulk capacitors (not shown in the schematic)
are fully charged.
are fully charged.
o
Soft-start circuit consisting of the external NMOS transistor Q4, TPS3803-
01 supervisory IC (SVS) and supporting passive components to provide 10
ms rise time for V
ms rise time for V
CCINT.
o
Soft-start circuit consisting of the external PMOS transistor Q3 and
supporting passive components to provide 10 ms rise time for V
CCO.
o
Sequential sequencing of V
CCINT,
V
CCAUX
then V
CCO.
§ the discrete SVS circuit formed by bipolar transistors Q1 and Q2
and supporting passives enables the V
CCAUX
regulator, U4.
§ V
CCAUX
enables the V
CCO
regulator, U3.
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-
The design meets Xilinx’s V
CCINT
and V
CCO
start- up profile requirements, where
applicable, including monotonic voltage ramp, in-rush current and power voltage
ramp time requirements.
ramp time requirements.
IMPORTANT WEB LINKS:
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Link to the TI home page for Xilinx FPGA power management solutions at
http://www.ti.com/xilinxfpga for more information and other reference designs.
http://www.ti.com/xilinxfpga for more information and other reference designs.