Texas Instruments TPS54395 Evaluation Module TPS54395EVM-057 TPS54395EVM-057 Scheda Tecnica
Codici prodotto
TPS54395EVM-057
Board Layout
5
Board Layout
This section provides a description of the TPS54395EVM, board layout, and layer illustrations.
5.1
Layout
The board layout for the TPS54395EVM is shown in
through
. The top layer contains
the main power traces for VIN and VOUTx. Also on the top layer are connections for the pins of the
TPS54395 and a large area filled with ground. Many of the signal traces also are located on the top side.
The input decoupling capacitors are located as close to the IC as possible. The input and output
connectors, test points, and all of the assembled components are located on the top side. An analog
ground (GND) area is provided on the top side. Analog ground (GND) and power ground (PGND) are
connected at a single point on the top layer near the IC. The other layers are primarily power ground but
the bottom layer has some traces to connect the test points for SSx and ENx.
TPS54395 and a large area filled with ground. Many of the signal traces also are located on the top side.
The input decoupling capacitors are located as close to the IC as possible. The input and output
connectors, test points, and all of the assembled components are located on the top side. An analog
ground (GND) area is provided on the top side. Analog ground (GND) and power ground (PGND) are
connected at a single point on the top layer near the IC. The other layers are primarily power ground but
the bottom layer has some traces to connect the test points for SSx and ENx.
Figure 20. Top Assembly
16
TPS54395 Dual Channel SWIFT™ Evaluation Module
SLVU703 – August 2012
Copyright © 2012, Texas Instruments Incorporated